We are truly living in the age of SoC design, where 78 percent of all designs today contain one or…
Language and Library Trends This blog is a continuation of a series of blogs that present the highlights from the…
Download the standard now – at no charge! The IEEE has published the latest update to the SystemVerilog standard. And…
OVM Bridges SystemVerilog and SystemC Languages When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog)…
Open-Source Proof-of-Concept Library Released Accellera Systems Initiative has released for general industry use an open-source proof-of-concept library as a companion…
Where might our paths cross? It is always challenge to fit all the needed visits in during the Design Automation…
In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should…
It is time to talk about what happens next with UVM The Design and Verification Conference (DVCon) has become the…
IEEE Std. 1666™-2011 Available as Free Download In November 2011 I blogged the IEEE Standards Association (SA) approved a revision…
