UVM: The Next IEEE Standard (1800.2)

UVM: The Next IEEE Standard (1800.2)

Accellera Handoffs UVM to IEEE It has been a long path from Mentor’s AVM to IEEE P1800.2.  But the moment…

Part 6: The 2014 Wilson Research Group Functional Verification Study

Part 6: The 2014 Wilson Research Group Functional Verification Study

FPGA Verification Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the…

DVCon India: A Smashing Hit!

DVCon India: A Smashing Hit!

DVCon India, held in September 2014 in Bangalore, built on the Indian SystemC User Group meeting events and added a…

Supporting A Season of Learning

Supporting A Season of Learning

From those just beginning to study electronic systems design to the practicing engineer, this is the time of the year…

More DVCon–More Mentor Tutorials!

More DVCon–More Mentor Tutorials!

As DVCon expands, we at Mentor Graphics have grown our sponsored sessions as well.  Would you expect less? In DVCon’s…

DVCon 2014: Standards on Display

DVCon 2014: Standards on Display

One of the nice things about DVCon is the update one can get from the developers of IEEE and Accellera…

STMicroelectronics: Simulation + Emulation = Verification Success

STMicroelectronics: Simulation + Emulation = Verification Success

We are truly living in the age of SoC design, where 78 percent of all designs today contain one or…

Part 8: The 2012 Wilson Research Group Functional Verification Study

Part 8: The 2012 Wilson Research Group Functional Verification Study

Language and Library Trends This blog is a continuation of a series of blogs that present the highlights from the…

IEEE 1800™-2012 SystemVerilog Standard Is Published

IEEE 1800™-2012 SystemVerilog Standard Is Published

Download the standard now – at no charge! The IEEE has published the latest update to the SystemVerilog standard.  And…