Simulation - Verification Horizons

FPGA Verification Effectiveness Trends This blog is a continuation of a series of blogs related to the 2014 Wilson Research…

FPGA Effort Verification Trends (Continued) This blog is a continuation of a series of blogs related to the 2014 Wilson…

FPGA Verification Effort Trends This blog is a continuation of a series of blogs related to the 2014 Wilson Research…

A colleague recently asked me: Has anything changed? Do design teams tape-out nowadays without GLS (Gate-Level Simulation)? And if so,…

FPGA Design Trends In my previous blog, I introduced the 2014 Wilson Research Group Functional Verification Study (click here). The objective…

This blog is a continuation of a series of blogs that present the highlights from the 2014 Wilson Research Group…

This is the first in a series of blogs that presents the findings from our new 2014 Wilson Research Group…

“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18. …

My Feb. 4 post introduced Mentor Graphics’ three-step FPGA verification process intended to help design teams get out of the…