Functional Verification - Verification Horizons

As vice-chair of the Accellera Portable Stimulus Working Group, it is my pleasure to announce that the Portable Test and…

FPGA Verification Effort Trends This blog is a continuation of a series of blogs related to the 2020 Wilson Research…

FPGA Verification Effectiveness In my previous blog, I present FPGA design trends identified in the 2020 Wilson Research Group Functional…

FPGA Design Trends In my previous blog, I introduced the 2020 Wilson Research Group Functional Verification Study (click here). The…

This blog is a continuation of a series of blogs that present the highlights from the 2020 Wilson Research Group…

This is the first in a sequence of blogs that presents the findings from our new 2020 Wilson Research Group…

As promised, here is my response to Siemens EDA’s SystemVerilog Race Condition Challenge. Race #1 Blocking and non-blocking assignments …

Between Accellera and the IEEE, there have been seven revisions of the SystemVerilog Language Reference Manual (LRM) over the past…

If there’s one thing I’ve learned since coming to Mentor early last year, it’s that the SystemVerilog language gives developers…