DAC 2020: A Rare Virtual Opportunity in Professional Development!

Probably one of the most important pieces of advice I ever received was given to me when I was a young undergraduate student by a chemistry professor. He told me, “Harry, there’s a big difference between knowing about something…and really knowing something.” This philosophy has always guided my professional development strategy starting from digital design and architecture, to formal and assertion-based techniques, and more recently to AI/ML solutions. With that said, I can’t think of a better opportunity than now to sharpen your own technical skills. Particularly since this year’s Design Automation Conference (DAC) is going virtual, which will provide broader access to engineers all over the world who would normally not have an opportunity to participate. In addition, this year’s virtual DAC is offered at an incredible deal with a significant decrease in registration cost while maintaining all the great technical content that has made DAC renowned.

The 57th DAC executive committee, together with ACM and IEEE, moved this year’s conference to a virtual event format scheduled for July 20-24, 2020. Rather than recreating the physical experience of a live conference (which is not possible virtually), the decision was made to focus on achieving DAC’s goals within a virtual environment, which are:

  • Provide a space to present cutting edge research
  • Provide a space for industry to showcase the latest products
  • Provide a an education forum
  • And even provide some virtual networking and fun opportunities

And I am very proud of what the team accomplished in putting together this year’s virtual event! In this blog I plan to highlight a few sessions worth checking out at this year’s conference.


Keynotes

Keynote: Semiconductor Technology: A System Perspective

DR. H.-S. Philip Wong
Chief Scientist
Taiwan Semiconductor Manufacturing Company Limited

Keynote: RISC-V Revolution and Momentum

Calista Redmond
Calista Redmond
CEO
RISC-V Foundation

Keynote: New Paradigms for 6G Wireless Communications

Andrea Goldsmith
Dr. Andrea Goldsmith
The Stephen Harris Professor
Stanford University

Mentor Participation

This year I am excited to announce that many of my Mentor colleagues are involved in the technical program, which I have highlighted below.

MONDAY July 20, 11:00am – 11:45am

Dr. Wally Rhines
CEO Emeritus
Mentor, a Siemens Business
  • Continuing Evolution of the Electronics Ecosystem
  • Abstract: The period starting in 2017 has witnessed a new wave in the evolution of electronic design automation.  Systems companies including automotive, aerospace and data center companies, have continued their move into the world of IC design. Restrictions on sales to Huawei, government programs to make China self-sufficient in semiconductor electronics and threats of further export restrictions have changed the outlook for the semiconductor industry. In addition, the application of new technologies like machine learning have ushered in a new wave of EDA capabilities.  Dr. Rhines will provide an electronics industry update and discuss future directions for EDA.

MONDAY July 20, 1:30pm – 3:00pm

  • Easy Deadlock Verification and Debug with Advanced Formal Verification
  • Best Paper Nominee***
  • Designer Track
  • Speaker: Laurent Arditi – Arm, Ltd., Valbonne, FranceAuthors: Laurent Arditi – Arm, Ltd., Valbonne, France, Vincent Abikhattar – Arm, Ltd., Sophia-Antipolis, France, Joe Hupcey III – Mentor, A Siemens Business, Fremont, CA, Jeremy Levitt – Mentor, A Siemens Business, Fremont, CA

TUESDAY July 21, 1:30pm – 3:00pm

TUESDAY July 21, 7:30am – 8:30am

  • Improving Transition-Coverage Cycle Time with a Declarative Description
  • Designer Track Poster
  • Speaker: Ashish Amonkar – Cypress Semiconductor Corp., Dublin, CA
  • Authors: Ashish Amonkar – Cypress Semiconductor Corp., Dublin, CA, Ammar Ahmad – Mentor, A Siemens Business, Fremont, CA, Matthew Ballance – Mentor, A Siemens Business, Wilsonville, OR

TUESDAY July 21, 7:30am – 8:30am

  • Improving Transition-Coverage Cycle Time with a Declarative Description
  • Designer Track Poster
  • Speaker: Ashish Amonkar – Cypress Semiconductor Corp., Dublin, CA
  • Authors: Ashish Amonkar – Cypress Semiconductor Corp., Dublin, CA, Ammar Ahmad – Mentor, A Siemens Business, Fremont, CA, Matthew Ballance – Mentor, A Siemens Business, Wilsonville, OR

TUESDAY July 21, 7:30am – 8:30am

TUESDAY July 21, 7:30am – 8:30am

TUESDAY July 21, 7:30am – 8:30am

TUESDAY July 21, 7:30am – 8:30am

TUESDAY July 21, 7:30am – 8:30am

  • Accelerating Early Design Physical Verification Cycle
  • Designer Track Poster
  • Speaker: Kalyana Kumar A – Advanced Micro Devices, Inc., Bengaluru, India
  • Authors: Kalyana Kumar A – Advanced Micro Devices, Inc., Bengaluru, India, Shah Vaishali – Advanced Micro Devices, Inc., Bangalore, India, DE2 Gokul R – Advanced Micro Devices, Inc., Bangalore, India, Nermeen Hossam – Mentor, A Siemens Business, Cairo, Egypt, Bhavani Prasad K – Mentor Graphics (India) Pvt. Ltd., Bangalore, India

TUESDAY July 21, 7:30am – 8:30am

  • Cross Products Hotspot Detection with Calibre SONR: A Machine Learning Technique

  • Designer Track Poster
  • Speaker: Haizhou Yin – GLOBALFOUNDRIES, Malta, NY
  • Authors: Haizhou Yin – GLOBALFOUNDRIES, Malta, NY, Yuansheng Ma – Mentor, A Siemens Business, Fremont, CA, Qian Xie – GLOBALFOUNDRIES, Malta, NY, Shaowen Gao – GLOBALFOUNDRIES, Malta, NY, Juli Opitz – Mentor, A Siemens Business, Fremont, CA, Rui Wu – Mentor, A Siemens Business, Wilsonville, OR, Le Hong – Mentor, A Siemens Business, Wilsonville, OR, Liang Cao – Mentor, A Siemens Business, Fremont, CA, Dingyi Hong – Mentor, A Siemens Business, Fremont, CA, Joerg Mellmann – Mentor, A Siemens Business, Wilsonville, OR, Panneerselvam Venkatachalam – GLOBALFOUNDRIES, Malta, NY, Yuyang Sun – Mentor, A Siemens Business, Wilsonville, OR, James Word – Mentor, A Siemens Business, Wilsonville, OR

TUESDAY July 21, 7:30am – 8:30am

WEDNESDAY July 22, 3:30pm – 5:00pm

  • How to Train Your Dragon Before You Have Machine Learning Training Data – A Litho Hotspot Validation Solution
  • Designer Track
  • Speaker: Joe Kwan – Mentor, A Siemens Business, Fremont, CA
  • Authors: Jae-Hyun Kang – Samsung Electronics Co., Ltd., Gyeonggi-do, Republic of Korea, Joe Kwan – Mentor, A Siemens Business, Fremont, CA, Namjae Kim – Samsung Electronics Co., Ltd., Gyeonggi-do, Republic of Korea, Jiwon Oh – Samsung Electronics Co., Ltd., Gyeonggi-do, Republic of Korea, Wael, ElManhawy – Mentor, A Siemens Business, Wilsonville, OR, Aliaa Kabeel – Mentor, A Siemens Business, Cairo, Egypt, Sarah Rizk – Mentor, A Siemens Business, Cairo, Egypt, Mohamed Ismail – Mentor, A Siemens Business, Cairo, Egypt, Kareem Madkour – Mentor, A Siemens Business, Cairo, Egypt

THURSDAY July 23, 3:30pm – 4:30pm

  • PANEL: High-Level Synthesis 1974 – 2020: The Meteoric Rise of a Hot Topic?
  • Research Track Panel
  • Moderator & Organizer:
    • Marilyn Wolf – Univ. of Nebraska, Lincoln, NE
  • Panelist:
    • Deming Chen – Univ. of Illinois at Urbana-Champaign, Urbana, IL
    • Ahmed Jerraya – CEA-LETI, Grenoble, France
    • Pierre Paulin – Synopsys, Inc., Mountain View, CA
    • Kazutoshi Wakabayashi – Univ. of Tokyo, Japan
    • Sean Dart, Cadence – ,San Jose, CA
    • Bryan Bowyer – Mentor, A Siemens Business, Wilsonville, OR
  • For a full listing of the technical program, visit this year’s Design Automation Conference website.

    I hope you take advantage of this rare opportunity in terms of professional development by participating in this year’s virtual DAC!

     

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