Assertions

Part 6: The 2020 Wilson Research Group Functional Verification Study

December 16, 2020

FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2020 Wilson…

By Harry Foster
4 MIN READ
The FPGA Verification Window Is Open

The FPGA Verification Window Is Open

May 7, 2014

My Feb. 4 post introduced Mentor Graphics’ three-step FPGA verification process intended to help design teams get out of the…

By Danny Santoro
1 MIN READ
Just because FPGAs are programmable doesn’t mean verification is dead

Just because FPGAs are programmable doesn’t mean verification is dead

February 4, 2014

Marketing teams at FPGA vendors have been busy as the silicon nanometer geometry race escalates. Altera is “delivering the unimaginable”…

By Danny Santoro
2 MIN READ
IEEE Approves Revised SystemVerilog Standard

IEEE Approves Revised SystemVerilog Standard

December 5, 2012

IEEE Std. 1800™-2012 Officially Ratified The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft…

By Dennis Brophy
3 MIN READ