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Free at Last! UVM1.0 is Here!

Free at Last! UVM1.0 is Here!

By now you’ve probably heard that Accellera approved the Universal Verification Methodology Standard (UVM1.0) today. This announcement is the culmination…

Parameterized Classes, Static Members and the Factory Macros

Parameterized Classes, Static Members and the Factory Macros

Somebody asked me a simple question: Why do need two different macros (`ovm_object_utils and `ovm_object_param_utils) to register classes with the…

IEEE Standards in India

IEEE Standards in India

IEEE Standards Association Hosts Design Automation Standardization Workshops in Bangalore & Delhi I, along with several other individuals, will participate…

Accellera Approves New Co-Emulation Standard

Accellera Approves New Co-Emulation Standard

Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the…

New Verification Horizons: Methodologies Don’t Have to be Scary

New Verification Horizons: Methodologies Don’t Have to be Scary

Hi Everyone, Just wanted to let you know that the latest edition of our Verification Horizons newsletter is available here….

The Survey Says: Verification Planning

The Survey Says: Verification Planning

As the saying goes: Those who fail to plan, plan to fail. With that said, I am excited to announce…

Towards UVM Register Package Interoperability

Towards UVM Register Package Interoperability

23rd Synopsys EDA Interoperability Forum Features a Verification Session with focus on the UVM Register Package As readers of the…

UVM: Giving Users What They Want

UVM: Giving Users What They Want

Technorati Tags: UVM,SystemVerilog,RAL,OVM The development of UVM in the Accellera VIP-TSC brings up, yet again, the age-old philosophical question: should…