Free at Last! UVM1.0 is Here!

By now you’ve probably heard that Accellera approved the Universal Verification Methodology Standard (UVM1.0) today. This announcement is the culmination of a great deal of work by the members of the Accellera Verification IP Technical Subcommittee (VIP_TSC), ably led by Tom Alsop of Intel and Hillel Miller of Freescale, and all who contributed to this outstanding effort should take a moment to bask in the glow of the accolades now flying around the blogosphere and twitterverse. To my colleagues on the VIP-TSC, I offer a hearty “Yo!” (sorry – inside joke) echoing those sentiments.

As a veteran of standards committees gong back to Verilog-95 (has it really been that long?), through Verilog 1364, SystemVerilog and now UVM, I’d like to offer my perspective. I have long been a proponent of Karen Bartleson’s First Rule of Standards, “Cooperate on standards; Compete on tools,” even before she had the brilliant idea of writing a book about it (which I strongly recommend, by the way). Having spent more time over the years than I care to recall trying to engage customers with new technology only to see them stuck where they are because of a mountain of proprietary code, I can’t tell you how much I’m looking forward to a level playing field. I expect that the user community is as well.

The value of standards has always been that a user can wrte one piece of code and use it across multiple tools to see which one is best. This is why Mentor has always been a strong supporter of standards, whether de facto, like OVM, or “official” standards from Accellera or IEEE. With UVM opening a new era of cooperation in the standards realm for functional verification, we invite our friends to join us in some healthy competition.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/verificationhorizons/2011/02/18/free-at-last-uvm10-is-here/