Thought Leadership

New Verification Horizons: Methodologies Don’t Have to be Scary

By Tom Fitzpatrick

Hi Everyone,

Just wanted to let you know that the latest edition of our Verification Horizons newsletter is available here. I’ll be blogging about some of the articles individually a bit later, but for now you can get an overview of the contents from reading my editor’s note. In addition to getting a taste of the articles, you’ll also learn how my daughter’s 10th birthday party was like an engineering project.

Here’s the Table of Contents:

Page 6…Survey Says: Verification Planning
by Harry Foster, Chief Verification Scientist Design Verification Technology,
Mentor Graphics Corporation

Page 8…Firmware Verification Using SystemVerilog OVM
by Ranga Kadambi, Eric Eu, and Sudheer Arey, Infineon Singapore
Mark Glasser and Christoph Suehnel, Mentor Graphics Corporation

Page 14…A SystemVerilog Configurable Coverage Model in an OVM setup
by Parag Goel, and Sakshi Bajaj, Applied Micro
with Pushkar Naik, Applied Micro
and Ashish Kumar, Mentor Graphics Corporation

Page 25…Advanced Techniques for AXI Bus Fabric Verification
by Alain Gonier and Jay O’Donnell, Mentor Graphics Corporation

Page 34…Converting Module-Based Verification Environments to Class-Based Using SystemVerilog OOP
by Amit Tanwar, Mentor Graphics Corporation

Partners’ Corner
Page 38…Verifying a CoFluent SystemC IP Model from a SystemVerilog UVM Testbench in Mentor Graphics Questa
by Laurent Isenegger, Jérôme Lemaitre and Wander Oliveira Cesário, CoFluent Design

Page 44…What You Need to Know About Dead-Code and X-Semantic Checks
by Ping Yeung and Erich Marschner, Mentor Graphics Corporation

I hope you enjoy this issue of Verification Horizons. If you’d like to register to receive future issues automatically (along with nearly 30,000 of your friends and colleagues), please click here.

Thanks for your support,
Tom Fitzpatrick
Editor, Verification Horizons

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This article first appeared on the Siemens Digital Industries Software blog at