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Get Ready for SystemVerilog 2012

Get Ready for SystemVerilog 2012

The latest revision of the IEEE 1800-2012 SystemVerilog Language Reference Manual (LRM) is about to hit the press; though I…

VHDL Update Comes to Verification Academy!

VHDL Update Comes to Verification Academy!

VHDL-2008 Explained Via 7 Course Modules For some time now a dedicated group of engineers have defined and standardized an…

IEEE Approves Revised SystemVerilog Standard

IEEE Approves Revised SystemVerilog Standard

IEEE Std. 1800™-2012 Officially Ratified The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft…

Coverage Cookbook Debuts

Coverage Cookbook Debuts

Verification Academy Adds Major New Technical Resource The Verification Academy adds another major methodology cookbook to focus on effective coverage…

IoT: Internet of Things

IoT: Internet of Things

Ready for 100 billion “things” connected by the Internet? The IEEE Standards Association (SA) Corporate Advisory Group (CAG) has been…

Check out the October, 2012 Verification Horizons

Check out the October, 2012 Verification Horizons

Hi Everyone, Just wanted to let you know that the latest and greatest edition of Verification Horizons is now available….

Improving simulation results with formal-based technology

Improving simulation results with formal-based technology

When it comes to formal methods, many engineers are skeptics. Perhaps this is due to value propositions that have been…

Introducing “Verification Academy 2.0”

Introducing “Verification Academy 2.0”

A new style takes center stage It was Fashion Week in Portland, Oregon in early October.  And while the thought…

OVM Gets Connected

OVM Gets Connected

OVM Bridges SystemVerilog and SystemC Languages When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog)…