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3 Notable Formal-Related Conference Papers of 2014

3 Notable Formal-Related Conference Papers of 2014

January 6, 2015

2014 was an exciting year for formal verification to say the least, and below I call out a sampling of…

By Joe Hupcey III
3 MIN READ
Latest Issue of Verification Horizons Available!

Latest Issue of Verification Horizons Available!

December 12, 2014

Just in time for Christmas and other year-end holidays, I am pleased to announce that the latest issue of Verification…

By Tom Fitzpatrick
2 MIN READ
SystemVerilog Testbench Debug – Are we having fun yet?

SystemVerilog Testbench Debug – Are we having fun yet?

November 24, 2014

SystemVerilog Testbench Debug – Are we having fun yet? Fun Debug should be fun. Watching waveforms march by, seeing ERRORS…

By Rich Edelman
3 MIN READ
ARM® Techcon Paper Report: How Microsoft Saved 4 Man-Months Meeting Their Coverage Closure Goals Using Automated Verification Management & Formal Apps

ARM® Techcon Paper Report: How Microsoft Saved 4 Man-Months Meeting Their Coverage Closure Goals Using Automated Verification Management & Formal Apps

November 17, 2014

Few verification tasks are more challenging than trying to achieve code coverage goals for a complex system that, by design,…

By Joe Hupcey III
4 MIN READ
Preparing for the Perfect Storm with New-School Verification Techniques

Preparing for the Perfect Storm with New-School Verification Techniques

November 5, 2014

Between 2006 and 2014, the average number of IPs integrated into an advanced SoC increased from about 30 to over…

By Matthew Ballance
2 MIN READ
On-Demand Webinar: UVM Sequences in Depth

On-Demand Webinar: UVM Sequences in Depth

November 5, 2014

When I was at DAC this year, I had a few folks come up to me at our Verification Academy…

By Tom Fitzpatrick
< 1 MIN READ
DVCon India: A Smashing Hit!

DVCon India: A Smashing Hit!

October 9, 2014

DVCon India, held in September 2014 in Bangalore, built on the Indian SystemC User Group meeting events and added a…

By Dennis Brophy
3 MIN READ
Portable and Productive Test Creation with Graph-Based Stimulus

Portable and Productive Test Creation with Graph-Based Stimulus

September 12, 2014

Verification engineers spend lots of time creating tests. In fact, creating enough tests to verify the design functionality consistently tops…

By Matthew Ballance
2 MIN READ
Supporting A Season of Learning

Supporting A Season of Learning

September 11, 2014

From those just beginning to study electronic systems design to the practicing engineer, this is the time of the year…

By Dennis Brophy
3 MIN READ