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NVMe – To the rescue of the Storage Revolution Bottleneck

NVMe – To the rescue of the Storage Revolution Bottleneck

“Between the dawn of civilization and 2003, we only created five exabytes; now we’re creating that amount every two days….

DVCon China 2018: Driving the Next Big Wave in Verification!

DVCon China 2018: Driving the Next Big Wave in Verification!

DVCon is recognized as the premiere industry-focused functional design and verification conference. In fact, today DVCon has grown from a…

OVL: The Free, Open Assertion Library You Can Use To Jump Start Your Formal Testbench

OVL: The Free, Open Assertion Library You Can Use To Jump Start Your Formal Testbench

You’ve watched all the Verification Academy videos on getting started with formal verification, and even tried some of the examples…

The New Verification Horizons is Here!

The New Verification Horizons is Here!

  Our March issue of Verification Horizons is now available here. Aside from giving me a chance to work through my…

New! Get your IEEE 1800-2017 SystemVerilog LRM at no charge

New! Get your IEEE 1800-2017 SystemVerilog LRM at no charge

Updated Feb 26, 2018: IEEE releases 1800-2017 Standard. Today at this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA)…

New and Improved SystemVerilog 1800-2017

New and Improved SystemVerilog 1800-2017

The IEEE-SA has a policy of keeping standards active by making sure they get a cycle of updates every 10…

Portable Test – Portable Intent, Portable Realization, or Both?

Portable Test – Portable Intent, Portable Realization, or Both?

The Accellera Portable Stimulus Working Group (PSWG) has been hard at work defining a language specification for capturing portable test…

Mentor Leads Portable Stimulus at DVCon US

Mentor Leads Portable Stimulus at DVCon US

I think I’ve mentioned before that DVCon (now DVCon US) is one of my favorite times of year. Having a…

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

[Preface: at the upcoming DVCon 2018 in San Jose, poster 4.12 addresses some of the issues raised below, as well…