Latest posts

Getting your Safety Architecture just right

Introduction In a recent industry survey, roughly 40% of ASIC and FPGA project starts had functional safety part of their…

The configurability dilemma creating safe ICs

A traditional automobile today consists of multiple systems controlling everything from the interior atmosphere to drive train to more advanced…

The importance of effective Safety Analysis

In the recent Wilson research industry survey, semiconductor companies reporting have made it clear that functional safety activities consume a…

The Many Flavors of Equivalence Checking: Part 6, FPGA-focused Equivalency Checking Flows

With last year’s acquisition of OneSpin, we now have a valuable addition to the solutions I described in The Many…

Lego Blocks

Odds and Ends

I hope that the Python for Verification Series has demonstrated that Python is a new tool in the verification team’s…

Logging in pyuvm

Logging in pyuvm This is part of the Python for Verification series of blog posts. The IEEE UVM specification (1800.2-2020)…

58th Design Automation Conference

Build Your Career by Attending the Static & Formal Verification University at DAC 2021

Among the reasons to go to university are the opportunities to open new career paths by learning new technical skills,…

The UVM Factory

In the previous post in the Python for Verification Series, we discussed how pyuvm implemented the configuration database as a…

My Motherboard

A UVM Scoreboard: Does it really have to be that hard?

UVM Scoreboards don’t have to be hard But I’m getting ahead of myself. This week I gave up on my…