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SystemVerilog Class Variables and Objects

Introduction How can you visualize the relationship between classes and objects in SystemVerilog? This is the first post in a…

Verification Academy UVM Video Courses Updated!

Two significant milestones were reached earlier this year. The first is that the Universal Verification Methodology (UVM) celebrated its 10-year…

Accellera FuSa WG: White paper released!

The Accellera Functional Safety Working Group was formed to address critical industry challenges suppliers, systems integrators and manufacturers face delivering…

Explanation of “Verification” in a DO-254 program

Often times, I’m asked to define what verification activities are required for a DO-254 program. For those experienced in a…

PCIe® Gen6 verification – the PCI Express® generation comes of age

Billions of us today – regardless of which Generation we belong to, Gen-X, Gen-Z, Millenials, Generation-Alpha – use PCI Express®…

Expediting Simulation Turn-around Time with Incremental Build Flows

Rapid simulation turn-around time is critical for high-functioning SoC teams because it enables a tight feedback cycle that teams use…

GSA Leadership Summit: New Paradigms – New Opportunities

Edge devices are generating data that needs to be analyzed in real time using machine learning or used to train models in the cloud. This GSA 2021 Silicon Leadership Summit session deep dives into innovations in the intelligent edge and the complexity of ensuring security.

Orchestrating an ISO26262 Fault Campaign

ISO26262 remains the state-of-the-art standard governing the activities required to prove electronics and electronic systems are safe for deployment in…

Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunting

DVCon U.S. 2021 Best Paper Report – Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt

This year’s DVCon U.S. saw many great papers, posters, and tutorials; covering almost every aspect of functional verification. Thus, in…