Tips & Tricks

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UVM Configuration DB Guidelines

UVM Configuration DB Guidelines

May 7, 2020

Introduction My previous blog posts were on static and parameterized classes to get you ready for the big game –…

By Chris Spear
3 MIN READ
SystemVerilog Static Methods

SystemVerilog Static Methods

April 29, 2020

Introduction In my last post, you learned how to create a class with a static property. This variable acts like…

By Chris Spear
2 MIN READ
SystemVerilog Classes with Static Properties

SystemVerilog Classes with Static Properties

April 21, 2020

Introduction One of the advantages of creating your testbenches with Object Oriented Programming, as opposed to traditional procedural programming, is…

By Chris Spear
2 MIN READ
SystemVerilog Parameterized Classes

SystemVerilog Parameterized Classes

April 16, 2020

SystemVerilog allows you to create modules and classes that are parameterized. This makes them more flexible, and able to work…

By Chris Spear
2 MIN READ
Tips for new UVM users

Tips for new UVM users

April 1, 2020

Or: What I forgot in class When I first learned UVM, there were many things that baffled me. What was…

By Chris Spear
3 MIN READ

The Many Flavors of Equivalence Checking: Part 3, How SLEC Brings Automated, Exhaustive Formal Analysis to Low Power Clock Gating Verification

March 23, 2020

[Preface / reminders: Part 1 of this series focused on synthesis validation with LEC and SLEC, and Part 2 describes…

By Joe Hupcey III
4 MIN READ

The Many Flavors of Equivalence Checking: Part 2, How SLEC Brings Automated, Exhaustive Formal Analysis to ECO/Bug Fix Verification

August 20, 2019

Perhaps the only Sequential Logic Equivalence Checking (SLEC) flow that is as common as the synthesis validation flow described in…

By Joe Hupcey III
3 MIN READ
The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

July 11, 2019

In EDA, the word “simulation” is used everywhere: there is RTL and gate level simulation, analog simulation, RF simulation, and…

By Joe Hupcey III
5 MIN READ
How to Reduce the Complexity of Formal Analysis – Part 5 – Memory Abstraction

How to Reduce the Complexity of Formal Analysis – Part 5 – Memory Abstraction

October 23, 2018

When big counters and memories are in the active logic cone of an assertion that keeps coming up as “inconclusive”,…

By Joe Hupcey III
4 MIN READ