A Short Class on SystemVerilog Classes

A Short Class on SystemVerilog Classes

It is often said that the English language is one of the most difficult languages to learn: inconsistent spelling rules;…

Part 5: The 2012 Wilson Research Group Functional Verification Study

Part 5: The 2012 Wilson Research Group Functional Verification Study

  Effort Spent in Verification This blog is a continuation of a series of blogs that present the highlights from…

Part 4: The 2012 Wilson Research Group Functional Verification Study

Part 4: The 2012 Wilson Research Group Functional Verification Study

Reuse Trends This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson…

Part 3: The 2012 Wilson Research Group Functional Verification Study

Part 3: The 2012 Wilson Research Group Functional Verification Study

Clocking and Power Trends In Part 2 of this series of blogs, I continued the discussion focused on design trends…

Part 2: The 2012 Wilson Research Group Functional Verification Study

Part 2: The 2012 Wilson Research Group Functional Verification Study

Design Trends (Continued) In Part 1 of this series of blogs, I focused on design trends (click here) as identified…

Texas-Sized DAC Edition of Verification Horizons Now Up on Verification Academy

Texas-Sized DAC Edition of Verification Horizons Now Up on Verification Academy

Hi Everyone, Just wanted to let you know that we just posted the PDF of the latest, Texas-Sized, DAC edition…

IEEE 1801™-2013 UPF Standard Is Published

IEEE 1801™-2013 UPF Standard Is Published

Download the standard now – at no charge The IEEE Standards Association (IEEE-SA) has published the latest UPF 2.1 standard,…

Part 1: The 2012 Wilson Research Group Functional Verification Study

Part 1: The 2012 Wilson Research Group Functional Verification Study

 Design Trends In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of…

What’s the deal with those wire’s and reg’s in Verilog

What’s the deal with those wire’s and reg’s in Verilog

A unique concept most beginners have trouble grasping about the Verilog, and now the SystemVerilog, Hardware Description Language (HDL) is…