Making formal property checking easy to use

For years one of the objectives in EDA has been to make formal property checking…

Redefining Verification Performance (Part 1)

What does the word performance mean to you? Speed? Well, obviously speed is an important…

SystemVerilog Coding Guidelines: Package import versus `include

Another frequently asked question: Should I import my classes from a package or `include them?…

The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)

Now that the Accellera VIP-TSC has released UVM-EA, effectively narrowing the choice of verification methodologies…

New Verification Academy Advanced OVM (&UVM) Module

I’ve always loved the Chinese proverb, “Give a man a fish and you feed him…

OVM/UVM @DAC: The Dog That Didn’t Bark

In the classic Sherlock Holmes story, “Silver Blaze,” Holmes realizes that the family dog didn’t…

DAC: Day 1; An Ode to an Old Friend

Denali Finale While I ponder the hundreds of partners I work with to support a…

UVM: Joint Statement Issued by Mentor, Cadence & Synopsys

DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys The full statement…

Static Verification

After spending years verifying ASICs with dynamic simulation, I started working on static verification 10…