One of the nice things about DVCon is the update one can get from the developers of IEEE and Accellera…
Marketing teams at FPGA vendors have been busy as the silicon nanometer geometry race escalates. Altera is “delivering the unimaginable”…
The UCIS Story There is no secret as design sizes grow it is doubly burdensome for verification. Two factors that…
Wow! I’ve been on the road since August, and finally found a spare moment to get back to this blog….
Wanted to let you all know that the October, 2013 issue of Verification Horizons is available online. You can view…
MENTOR GRAPHICS AT ARM TECHCON This week ARM® TechCon® 2013 is being held at the Santa Clara Convention Center from…
Low Power Flow Kicks-off Symposium In the world of electronic design automation, as an idea takes hold and works its…
We are truly living in the age of SoC design, where 78 percent of all designs today contain one or…
It’s hard for me to believe that SystemVerilog 3.1 was released just over 10 years ago. The 3.1 version added…
