I was fortunate to be able to attend DVCon this year. One of my favorite aspects of the DVCon show…
Do automated formal apps really help D&V engineers “cross the chasm” and start using formal verification directly? In Part 1…
One of the biggest developments in the formal verification world in the past several years has been the industry-wide growth…
It is always good to pause to recognize the companies and individuals with whom we collaborate to create the verification…
FPGA Effort Verification Trends (Continued) This blog is a continuation of a series of blogs related to the 2014 Wilson…
With a name like “Fitzpatrick,” you knew I’d be celebrating today, right? Well, there’s no better way to celebrate this…
FPGA Verification Effort Trends This blog is a continuation of a series of blogs related to the 2014 Wilson Research…
A colleague recently asked me: Has anything changed? Do design teams tape-out nowadays without GLS (Gate-Level Simulation)? And if so,…
It’s my favorite time of year again—DVCon! And I believe that the DVCon 2015 technical program committee has put together…
