Thought Leadership

Beating Design Complexity with VirtuaLAB

By Lauro Rizzatti

Content delivery through the Internet gateway is ever changing and evolving. Today’s mechanism for delivery is more efficient, less power consuming, and better performing than previous generations. Competition is fierce for companies who want to support this gateway. It’s a crowded field and the chips driving high-capacity networks are large and massively complex.  In fact, these network switches and routers routinely have more than 500,000 gates. Project teams aim for a large number of ports, expanded throughput, while decreasing latency and beefing up security and ease of use.

Verifying the design of these chips requires a broad set of verification solutions, including hardware emulation. One verification team recently used hardware emulation in an in-circuit-emulation (ICE) mode to test a SoC design with a 128-port Ethernet interface, and a variable bandwidth of 1/10/40/100/120Gbps. This team elected to use hardware emulation because it could test a design with real traffic with one Ethernet tester per port. A speed rate adapter was inserted between the fast tester and the slow emulated design under test (DUT) since a direct connection is not possible due to rather different speed domains. The setup had 128 Ethernet testers, 128 Ethernet speed adapters and heaps of cables. Sadly, the entire setup could only support a single user who used the setup in an emulation lab.

Another verification team took an entirely different approach using the Mentor Ethernet VirtuaLAB, where Ethernet testers are modeled in software running under Linux on a workstation connected to the emulator. The model, an accurate representation of the actual physical tester, is based on intellectual property (IP) blocks that have already been implemented.

The virtual tester includes an Ethernet Packet Generator and Monitor (EPGM) that generates, transmits and monitors Ethernet packets within the DUT and can configure GMII, XGMII, XLGMII/CGMII and CXGMII interfaces for 1G, 10G, 40G/100G and 120G. VirtuaLAB software conducts off-line analysis of the traffic, provides statistics, and supports a variety of other functions.

An interface between the VirtuaLAB virtual tester and the DUT has one instance of VirtuaLAB-DPI communicating to a Virtual Ethernet xRTL (extended Register Transfer Level) transactor connected to a Null-PHY linked to the DUT. One xRTL transactor is required for each port of any xMII supported type.

Multiple VirtuaLAB applications can be bundled together across multiple workstations–– known as a multi co-model –– to support large port-count configurations. High Speed Link (HSL) cards are used to connect co-model channels from workstations to the emulator. This tightly integrated transport mechanism is tuned for maximum wall clock performance and transparent to the testbench. Data plane emulation throughput scales linearly with the port count because of this parallel runtime and debug architecture.

Reconfiguring the virtual tester to perform various functions is done through remote access to a workstation, a stable and reliable piece of equipment less costly than a complex Ethernet tester with equivalent functionality. It has the ability to concurrently support multiple users. VirtuaLAB can be used as an enterprise-wide resource in a datacenter, using Enterprise Server’s IT management capabilities.

If you want to know more, download the Accelerating Networking Products to Market Using Ethernet VirtuaLAB whitepaper

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This article first appeared on the Siemens Digital Industries Software blog at