Latest posts

Improve defect detection for competitive, high-quality SoCs

To deliver the highest quality SoCs, these manufacturing test strategies ensure defects are detected before it’s too late. It is…

Introducing Tessent Streaming Scan Network

Slash test costs and reduce implementation effort for complex next-generation SoCs. IC engineering teams have seen a dramatic rise in…

Tessent’s ITC 2020 wrap-up

The International Test Conference carried on this year as a virtual event. It’s a difficult format to make work, but…

DFT and the competitive edge

Advanced DFT is your competitive edge Every new SoC project starts with grand hopes of glory. This one will be…

Tessent Wraps Up Summer Webinar Series

The summer of 2020 featured several new webinars from the Tessent Test Solutions group at Mentor, a Siemens business. These…

Video: ITC India 2020 keynote—Test community can take on silicon lifecycle challenges

The role of test is expanding from its traditional role into one that includes managing the entire silicon lifecycle. To…

Using critical area to optimize test patterns

Using critical area to optimize test patterns

In a new technical paper, Ron Press, the director of technology enablement for the Tessent Test Solutions, describes the new…

DFT Seminar: Using critical-area weighted optimization for more effective test patterns

DFT Seminar: Using critical-area weighted optimization for more effective test patterns

The world of ATPG just changed with the introduction of a new solution that can calculate the critical-area effectiveness of…

Tune in to ITC India 2020

Tune in to ITC India 2020

Mentor’s Tessent group is excited to participate in ITC India on July 12-14, 2020. While it is a virtual event…