Semiconductors

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System-level, post-layout electrical analysis for high-density advanced packaging (HDAP)

December 18, 2023

HDAP designs like FOWLP need post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification DRC and LVS.

By John McMillan
3 MIN READ

Crossing the chasm: Bringing SoC and package verification together

December 8, 2023

3D IC package designers need assembly-level LVS for HDAP verification.

By John McMillan
2 MIN READ

Package designers need assembly-level LVS for HDAP verification

December 5, 2023

While advanced integrated circuit (IC) packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique…

By John McMillan
2 MIN READ
An image of an IC package design in Xpedition Package Designer with text that says: Achieving substrate supplier fabrication requirements: a designer's guide

Achieving substrate supplier fabrication requirements: a designer’s guide

December 5, 2023

Designing advanced package layouts with large areas of metal can be a daunting task, given the stringent requirements imposed by…

By Keith Felton
3 MIN READ

Understanding 3D IC Technology: Unveiling the Future of Integrated Circuits

November 6, 2023

Delve into the world of 3D IC technology, its architecture, benefits, and applications. Learn how it’s reshaping the future of integrated circuits for enhanced performance and efficiency.

By John McMillan
6 MIN READ
Image of chiplets with text onscreen saying HBM

High Bandwidth Memory (HBM): Unleashing the power of next-gen memory technology

September 28, 2023

In the ever-evolving realm of semiconductor technology, one innovation stands out above the rest: High Bandwidth Memory (HBM). Offering unparalleled…

By Edward Hudson
3 MIN READ
Image of an IC package design with text that says A workflow methodology for homogeneous disaggregation using hierarchical device planning

A workflow methodology for homogeneous disaggregation using hierarchical device planning

July 20, 2023

Advancements in IC packaging manufacturing, combined with the exploding costs of designing monolithic ICs on today’s advanced process nodes, have…

By Chris Cone
5 MIN READ
Illustration of an IC Package design with text that says Why are you spending 30%+ more time on semiconductor packaging design?

Why are you spending 30%+ more time on semiconductor packaging design?

May 18, 2023

Designs are just getting bigger and more complex Yes, an obvious aspect is increasing design complexity. Packages are now a…

By Keith Felton
2 MIN READ
Illustration of 3D IC design workflows

Why co-design-driven semiconductor package planning and prototyping is critical for design success

April 20, 2023

The connectivity management complexity of package assemblies where multiple chiplets/ASICs and memory are heterogeneously integrated, introduces a great deal of…

By Keith Felton
3 MIN READ