3DSTACK - Semiconductor Packaging

2.5D vs. 3D IC: which chip packaging technology is right for you?

June 24, 2025

Why 2.5D vs. 3D IC matters in modern chip design As semiconductor innovation pushes the limits of Moore’s Law, traditional…

By John McMillan

6 MIN READ

3D IC rendering illustrating advanced chip packaging with vertically stacked dies

Chip packaging explained: From IC packaging basics to advanced 2.5D and 3D IC technologies

June 5, 2025

Understanding the evolution and importance of chip packaging As semiconductor innovation pushes the boundaries of performance and power efficiency, chip…

By John McMillan

6 MIN READ

User2User 2024: Meeting future performance demands through packaging: ChipletZ

September 27, 2024

Learn how 3DIC tech enhances compact, high-performance systems but faces verification challenges. We explore solutions and methodologies, including the use of Siemens XSI and Calibre 3DSTACK.

By John McMillan

4 MIN READ

User2User 2024: EMIB based advanced packaging flow – Intel Foundry

August 12, 2024

Learn how Intel uses 3DIC verification to leverage Siemens XSI & Calibre 3DSTACK for DRC, LVS, assembly checks. Explore methodologies for high-performance systems.

By John McMillan

3 MIN READ

Assembly Verification Flow for Silicon Interposers with Embedded Deep Trench Capacitance

User2User 2024: Assembly verification flow for silicon interposers

July 15, 2024

In this User2User 2024 session Broadcom’s Suvarna Vikhankar presents “Assembly Verification Flow for Silicon Interposers with Embedded Deep Trench Capacitance”

By John McMillan

2 MIN READ

User2User 2024: Advanced physical verification flows for 3D IC’s

June 25, 2024

In this User2User 2024 video presentation, now available on-demand, Microsoft’s Amit Kumar discusses 3D IC verification flows with a focus…

By John McMillan

3 MIN READ