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User2User 2024: EMIB based advanced packaging flow – Intel Foundry

August 12, 2024

Learn how Intel uses 3DIC verification to leverage Siemens XSI & Calibre 3DSTACK for DRC, LVS, assembly checks. Explore methodologies for high-performance systems.

By John McMillan
3 MIN READ

The multi-physics challenge: Known good die may not behave in 3D IC as stand alone!

August 5, 2024

Discover how Siemens’ EDA tackles the multi-physics challenge to achieve fast, accurate assembly-level physical verification.

By John McMillan
2 MIN READ
Image showing physical design IP reuse with Xpedition Package designer

Embracing physical design IP reuse as a best practice

July 22, 2024

Efficiency in IC package design is becoming more important as design cycles shorten and complexity surges. One common approach to…

By Keith Felton
2 MIN READ
Advanced Physical Verification Flows for 3DICs

User2User 2024: Advanced physical verification flows for 3D IC’s

June 25, 2024

In this User2User 2024 video presentation, now available on-demand, Microsoft’s Amit Kumar discusses 3D IC verification flows with a focus…

By John McMillan
3 MIN READ
New innovative way to functionally verify heterogeneous 2D/3D package connectivity

New innovative way to functionally verify heterogeneous 2D/3D package connectivity

June 6, 2024

This blog introduces a white paper that addresses the challenges of verifying
package connectivity and illustrated how to use formal tools to verify connectivity for package designs.

By John McMillan and Todd Burkholder
3 MIN READ
Two people working at a white board with text onscreen that says: Multiplying engineering resources for efficient package substrate design

Multiplying engineering resources for efficient package substrate design

May 14, 2024

In the world of package substrate design, the age-old saying, “many hands make light work,” holds more truth than ever….

By Keith Felton
2 MIN READ
Image of a chip with text that says: High Bandwidth Memory integration

Managing the complexities of High Bandwidth Memory integration in high-performance computing

March 12, 2024

The utilization of High Bandwidth Memory (HBM) has become a cornerstone for high performance computing (HPC) CPUs, GPUs, and AI…

By Keith Felton
2 MIN READ
Taking 2.5D/3D IC physical verification to the next level

Taking 2.5D/3D IC physical verification to the next level

February 21, 2024

Taking 2.5D/3D IC physical verification to the next level. As package designs continue to evolve, so must the verification requirements. Designers working on even the most complex multi-die, multi-chiplet stacked configurations require enhanced checking capabilities to quickly and easily verify that the physical die are placed correctly to ensure proper connectivity and electrical behavior.

By John McMillan
4 MIN READ

A deep dive into HDAP LVS/LVL verification

January 29, 2024

EDA companies are developing tools and workflows to support HDAP (High-density advanced packaging) LVS/LVL verification. Though the data for achieving “signoff-level” confidence is a work in progress, EDA companies are providing tools that can adapt to different levels of data availability and enable HDAP designers to execute HDAP LVS/LVL flows that are both productive and beneficial.

By John McMillan
4 MIN READ