Six Key Trends Redefining 3D IC Packaging in the AI Era
Some say we are officially in the Post-Moore’s Law world. Moore himself closed his seminal paper1 by mentioning the “day of reckoning” and said, “it may prove to be more economical to build large systems out of smaller functions…”
Labels aside, one truth is undeniable; the pace of innovation in chiplets and advanced packaging is accelerating, driving 3D IC technologies into the mainstream and rewriting the rules IC and package teams have relied upon for decades.
Read on to explore six key trends driving this shift and how Siemens helps leading teams evolve their design workflows to accelerate 3D IC innovations. You can also watch our recent LinkedIn Live event for a deeper dive into practical strategies, from early pathfinding to STCO.
Why is advanced packaging a key enabler for AI performance scaling?
Between 2012 and 2018, AI compute demand doubled every 3.4 months. More recently, this pace has slowed down to doubling every 7 months. This is pushing transistor density and bandwidth demand beyond what monolithic SoCs can deliver. At the same time, the industry has run into a fundamental physical limit for feature sizes. Advanced lithography caps reticle size at roughly 858 mm², the largest mask pattern that can be printed on a wafer; however, increased defectivity and poor yield in advanced technology nodes require dies to be much smaller to be economically viable. Side-by-side integration of split dies in 2.5D advanced packages is approaching the limits of die-to-die interface technology, as well as the form-factor limits of end systems.
As a result, scaling next-generation AI and HPC systems requires a fundamental shift in architecture – where performance gains come from proximity in three dimensions. Logic and memory must be disaggregated, then re-integrated across wafers, vertical stacks and advanced packages, while ensuring thermal, electrical and mechanical reliability.
Trend 1: Technology scale-down and integration scale-out
The roadmap for advanced packaging is pursuing feature size reduction for higher integration density for better performance at lower power. As thermal-compressed bonds reach their integration limits, hybrid bonds will drive the 3D interconnect to 1um and below. Additionally, AI and HPC compute suppliers are considering wafer- and panel- level architecture for ever more compute closer together.
One industrial example is Cerebras with its WSE-3 accelerator, integrating roughly 4 trillion transistors across a ~215 × 215 mm active area. Meanwhile, foundries are pursuing more modular wafer-scale strategies. TSMC’s SoW-X assembles pre-tested logic, memory and I/O dies onto a reconstructed wafer using wafer-wide redistribution layers (RDLs) and local silicon interconnects (LSI), with disclosed targets of up to 16 full-reticle ASICs and ~80 HBM4 stacks.
Consequently, EDA requirements are shifting toward wafer-scale, multiphysics system simulation to accurately model power, thermal, signal and mechanical interactions across highly integrated architectures.
Trend 2: Let there be light: Unlock 3D CPO for AI systems
Optical interconnects, with their low attenuation over long distances, are integral to data-center-scale compute engines and beyond. As AI systems continue to scale, power consumption from high-speed electrical links is rising while bandwidth density approaches physical limits.
Co-packaged optics (CPO) has emerged as a key enabler for next-generation AI performance by tightly integrating electronic ICs (EICs) and photonic ICs (PICs) within the same package. By moving optical I/O closer to the xPU or switch silicon, CPO shortens link distance from tens of centimeters to millimeters, improving signal integrity and bandwidth density.
Foundries and OSATs are already proving that this level of integration is practical. Platforms such as TSMC’s Compact Universal Photonic Engine (COUPE) demonstrate how electronic dies can be stacked directly on photonic dies using advanced 3D packaging.
From a design perspective, CPO raises the bar for device validation and testing. In 3D architecture, hybrid bonding, die thinning and vertical heat flow introduce complex thermo-mechanical stresses that can impact alignment accuracy and long-term reliability. Thermal-optical effects need to be analyzed carefully due to the effect of heat on wavelength shift.
Trend 3: Cooling silicon “skyscrapers” with microfluidics inside the package
By stacking more memory vertically as a multi-layer “silicon skyscraper,” designers can shorten interconnect lengths, enabling higher bandwidth without going laterally across the package. The challenge is that DRAM is far more temperature-sensitive than logic. While advanced logic dies can operate up to 125 °C, DRAM is often limited to 85 °C. As memory moves closer in a stacked system, thermal headroom quickly becomes the dominant design concern. Keeping HBM within spec while sustaining high logic power density requires a more aggressive cooling strategy.
Emerging microfluidic approaches address this challenge by directly bringing coolant micrometers from active transistors. Micro-scale trenches or channels are etched to increase contact area, significantly improving heat transfer efficiency.
As cooling becomes an integral part of the package architecture, accurate 3D models of micro-channel networks are essential, along with multiphysics solvers capable of handling coupled electrical, thermal and mechanical effects.
Trend 4: Material innovations advancing AI, HPC and 6G applications
Recent strides in manufacturing and materials science have significantly advanced semiconductor chip and electronics packaging.
First, glass substrates are gaining momentum for large-area and high-frequency designs. Mechanically, glass offers a coefficient of thermal expansion (~3.2 ppm/°C) close to silicon, helping reduce package warpage by nearly 50% in large substrates. Electrically, its low dielectric constant supports reliable signaling as data rates approach 224 Gbps and RF frequencies move toward 100 GHz for 6G systems. Manufacturing advances such as Laser-Induced Deep Etching (LIDE) and fine-pitch through-glass vias (TGVs) make glass increasingly practical for heterogeneous integration of high-frequency front-end chips, antennas and low-loss interconnects.
However, glass is brittle. As substrates are thinned to meet electrical and form-factor requirements, interface stress, fracture risk and stress decoupling across layers become first-order design concerns. Accurately modeling these effects early on will be paramount.
Second, polymer-based packaging materials, once viewed as little more than a means to glue or encase the chip, have now emerged as important factors for reliability, performance, and cost. As chips move to chiplets, 2.5D and 3D stacks, mechanical stress becomes the real challenge. Polymers are what absorbs them and, without them, yield collapses and reliability fails.
Trend 5: Rising need for mmWave antenna-in-package design
As the industry progresses 6G research and prototyping, adoption of antenna-in-package (AiP) will reach an inflection point.
Operations in the sub-THz and >100 GHz regimes impose fundamental constraints on interconnect loss, antenna efficiency and phase accuracy. As wavelengths shrink dramatically, antenna elements become small enough to be integrated directly inside the package. This enables dense phased-array architectures with advanced beamforming, tighter RF-to-antenna coupling, and lower losses by eliminating board-level routing.
Recent AiP architectures increasingly leverage vertical, 3D integration. Multiple dielectric layers, embedded ground planes and parasitic elements are stacked within microns of the RF IC. This approach minimizes electrical path length, suppresses parasitic loss and avoids PCB-level feedline attenuation.
However, integrating antennas into the package significantly tightens manufacturing and design tolerances. At sub-THz frequencies, micron-scale variations in dielectric thickness, surface roughness, via geometry, or layer alignment can measurably degrade system efficiency, bandwidth and beamforming accuracy. The proximity of RF, digital logic and power delivery networks increases susceptibility to coupling, EMI/EMC issues and thermally induced RF drift.
Trend 6: 3D AI for 3D IC design
As 3D IC complexity accelerates, traditional rule-based automation and point optimizers are no longer sufficient to manage the scale, coupling, and design-space explosion that advanced packaging introduces. This is driving a new shift toward AI-native workflows purpose-built for 3D ICs, where large language models (LLMs), optimization engines, and domain-specific AI operate across the full lifecycle of design, analysis, and validation. Leading EDA vendors like Siemens are already applying AI to design exploration, routing, multiphysics optimization, DFT and more.
The next step is orchestration powered by generative and agentic AI. For instance, in early architecture phases, LLMs can convert human-readable inputs (PDF specs, requirements, intent) into structured, machine-ready formats such as, allowing teams to move from intent to executable analysis in hours rather than weeks.
During implementation, AI can help accelerate exploration of vast design spaces across stacks and packages, learning from prior designs to converge faster under real manufacturing constraints.
At signoff, LLMs synthesize cross-domain results into concise, auditable summaries that capture rationale, margins, and residual risk, closing the loop between analysis and decision-making.
This “3D AI” paradigm is not about replacing engineers but scaling human expertise to explore more options earlier, converge faster, and make decisions with deeper insights.
Conclusion
In the 3D IC era, system complexity is skyrocketing.
Designers now have more factors to reason about – material choices, architectural decisions, and tightly coupled interactions across electrical, thermal, and mechanical domains, with far less margin for late-stage correction. Getting key trade-offs right earlier in the flow has become essential.
At Siemens, the focus is on helping 3D IC design teams manage that complexity through multiphysics-aware, die-to-system design flows powered by AI. These workflows are built to provide earlier visibility into cross-domain interactions, so engineers can understand the implications of their decisions sooner and evaluate alternatives with confidence.
If you’re rethinking how your design flow needs to evolve to handle emerging 3D IC challenges, Siemens can help you explore options quickly and identify risks earlier. Let’s start with the problems you’re seeing, schedule a free consultation with us today.
References:
- “Cramming more components onto Integrated Circuits” – Gordon Moore, 1965 ↩︎
