John McMillan (00:01.71)

Hello and welcome to the Siemens 3D IC podcast series where we dive into the exciting world of semiconductor, chiplet integration and advanced technology platforms using 2.5 and 3D techniques brought to you by the Siemens Thought Leadership Team. I’m your host, John McMillan. In this podcast series, I’ve talked with industry leaders and subject matter experts to discuss the latest on 3D IC, chiplet ecosystems, industry trends and roadmaps.

And in today’s podcast, we’re gonna talk about SI/PI, that’s Signal Integrity and Power Integrity Analysis in 3D IC Design. And I’m excited to welcome my guest, John Caka, a principal SI/PI engineer at Siemens EDA. Welcome, John. And before we dive into today’s discussion, please tell our listeners a little about yourself and your current role.

John Caka (00:45.982)

Absolutely. Thanks, John. So my name is John Caka. I’ve been with Siemens for roughly six years in a couple of different roles. When I first joined, I was doing kind of more customer support. Any one that runs any sort of Siemens software in the high speed signal and power integrity domain had access to kind of that support. A few years ago, I switched to a more kind of pre-sales field role where I’ve really been able to get in, know, close with the customers upfront, understand their design challenges, provide them solutions. Like I said, all in the context of signal and power integrity. Prior to that, I was a signal and power integrity designer at Micron Technology for about 7-8 years.

John McMillan (01:38.798)

So for our new listeners or people who aren’t familiar with what SI/PI are, what is SI/PI and why is it important?

John Caka (01:49.006)

Absolutely. So that’s a great question, John. You know, really signal and power integrity, can boil it down to a couple key points. It’s basically we’re talking about how we reliably transmit signals from a driver to a receiver. Signal integrity itself, we’re focusing mainly on maintaining our signal fidelity. So we’re looking at things like eye diagrams, eye height, eye width. In the frequency domain, we’re looking at things like insertion loss, return loss, crosstalk, and trying to identify issues in the design that would prevent an open eye. At the end of the day, that’s kind of the key metric that we’re looking for.

For power integrity, it’s a little bit different. A lot of… You know, for signals, a lot of the signals that we’re running have a specific spec or protocol. We kind of know what we need to, we know the targets we need to hit. They’ve been well studied and well identified. For power integrity, it can become a little more hand wavy. It’s very dependent on that, you know, the individual customers die requirements. So really it’s about being able to provide stable, clean power at the die pads, at the BGA balls, anywhere throughout the system. But like I said, it’s much more constrained kind of to the individual customer challenge, not necessarily like spec’d out at an industry level.

John McMillan (03:34.51)

Gotcha, so is there a differentiation between what we normally see in a traditional SI/PI flow and what we would see in a flow for 3D IC?

John Caka (03:47.502)

Absolutely. So if you think about the context of a monolithic SoC into kind of a PCB system, basically we’re looking at kind of one component level device into a system. And then we can perform that component level analysis on the package, you know, a monolithic SoC, we can do the power demand analysis. We can run our signal integrity analysis, validate the different signals and channels.

And then kind of in parallel to that, we can work on the PCB. So typically that’s set up as two separate teams, right? You’ve got a packaging team, a PCB team. You kind of work in parallel, understanding some design trade-offs. Maybe there’s some timing margin or maybe there’s some voltage margin that we can steal from the PCB side if the routing is constrained on the package or vice versa.

For 3D ICs, it’s… it’s much more of a flat design process, right? Because basically we’re taking a very large system and we’re condensing it down. So it doesn’t really look like a traditional monolithic die, it doesn’t look like a monolithic package. The architectures are all different and it’s really a set of kind of mini subsystems. So the analysis that you have to do really has to be straight early on. And really analyze all the different pieces of the subsystem concurrently if you can, or waiting for the correct inputs.

But yeah, like I said, the traditional flow is you’ve got the one component or several components. We validate that. We validate the system. For 3D IC, we’re having to do everything at once. And that doesn’t even bring into conversation yet the kind of multi-physics problems that we run into in 3D IC. In a traditional package, say, thermal may be a concern, but you’ve got plenty of real estate for degassing holes. You’ve got typically plenty of space for your power domain. So it’s a concern, but not a foremost concern in 3D IC.

John Caka (06:12.458)

Absolutely not. You’re having to think about your thermal concerns right alongside your power concerns right alongside your signal routing density. You can’t really disaggregate the construction of that. You have to run everything in parallel and really validate the system as you go with the inputs you have.

John McMillan (06:40.984)

Gotcha.

John McMillan (06:45.496)

Can you describe progressive verification as a strategy to address different analysis requirements at different stages?

John Caka (06:53.87)

Yeah, absolutely. So you can think of progressive verification as something, it’s a principle at Siemens we take very seriously. And basically the thought process behind progressive verification is when you start a design, you may not have very much information related to that design. So how does this look in the context of a 2.5D heterogeneous integration or a true 3D IC package?

We’re doing some early analysis where we’re looking at possibly some architectural feasibility studies. Maybe we’ve got some rough numbers for our power budget. We’re starting to put into place what interfaces are we going to have in this system. So we can start to do some early analysis with just those base level inputs.

We can do some pre-layout signal integrity analysis where we basically put down representative interconnect, let’s say, for an interconnect bridge. If we know there’s going to be a bridge in our system, let’s lay out those dimensions for that bridge in a pre-layout standpoint and put an envelope. This is what we can build. This is what will work at these speed grades. We’re already starting off at a good place.

Then we kind of move on to floor planning real implementation. We take those guidelines that we did from our early analysis, implement those into an actual layout. And there we can start to do kind of, you know, more in-depth analysis where we may have a base layout for a power grid. So we can start looking at our PDN requirements. We can start looking at verification of our actual signal paths, you know, with the different components hooked up. You can even start to do some optimization of these structures, right? So once you get some routing down, we run the analysis, we say, hey, can we improve this? And obviously, you know, this is something we can talk about more, but this is one difference, you know, in the context of 3D ICs to kind of monolithic SoC designs.

John Caka (09:18.078)

is part in the die-to-die standards. And right now we’re kind of in the nascency of these die-to-die standards. So looking at things like UCIE, BOW, AIB, different die-to-die protocols that are really in their nascency compared to established protocols like DDR or PCIe. So it gives the engineers a lot of flexibility because there’s some ambiguity in the spec.

So this early analysis becomes even more critical and kind of the final the final stage John of this progressive verification. You’ve gone through your early analysis. You’ve gone through kind of some implementation, maybe some improvement the last step is okay. Let’s get actual vendor specific IP if we have it available at this point. Let’s do detailed electrical analysis of our signal of our critical signal paths. Let’s do detailed S-parameter models of our impedance network. Let’s start feeding that with our actual current values that we’re getting from our different stakeholders, the die designers, and really kind of put a full closure. So that’s the thought behind that progressive verification is start as early as you can with as few inputs as you can to get yourself on the right path to make that final verification step just basically a check mark.

John McMillan (10:18.158)

Let’s get it

John McMillan (10:49.294)

Gotcha. It sounds like there are a lot of stakeholders involved here. Who are they and how is it challenging them?

John Caka (10:59.168)

Yeah, mean, absolutely. So if you’re, if you’re thinking about, you know, a 3D IC design, which to think about some of the personas that are involved, right? So we’ll have system architects. They’re going to be looking at floor planning. How many different subsystems are we going to have in this, you know, in this chiplet ecosystem? How many kind of baseband side dies are we going to have? How many communication channels do we need?

We also have obviously the die designers, right? They’re going to be key stakeholders in this that are running the actual individual die architecture, running the IO planning. Thinking about things like the power distribution within each individual die and communicating what those requirements are.

Then you have the layout team that’s responsible on both the die side, the substrate side. If there’s any sort of, you know, silicon interconnect, you know, any sort of bridge that could potentially be a different layout team. So we’ve got different levels of, you know, designers, architects, different levels of layout from the die all the way to kind of the more traditional, you know, packaging PCB layout side of the teams.

And then you have also the analysis side, you know, the analysis and verification, the SI/PI teams that are providing guidelines at all these different levels. You’re giving bump out advice to the system architects for the die floor plan, right? For the die designers, it’s saying, okay, do you really need that many power and ground bumps or can we swap some out? Again, using that whole kind of progressive methodology standpoint where the earlier you get these different stakeholders talking together, the easier it is to going to be to build something that actually works. Know, and then one last level, you know, I talked about multi-physics a little bit, but you’ve also got different mechanical stresses that are a concern here. So you’ve got mechanical teams, you’ve got thermal teams, you’ve got the electrical teams, you’ve got a lot of different

John Caka (13:22.284)

kind of pieces of the equation that all have to come together for successful design.

John McMillan (13:30.058)

It sounds like a really collaborative process. Switching gears a little bit, recently, Chipletz a fabless substrate startup selected Siemens as a strategic EDA provider for the development of its smart substrate products. Can you tell us more about that Chipletz story?

John Caka (13:34.741)

Absolutely.

John Caka (13:51.126)

Yeah, absolutely. So I had the opportunity to work quite a bit with Chipletz as they were selecting their vendors for both die layout tools, basically the whole portfolio. They needed to find a vendor that could support their 3DIC design. And it was really interesting initially, right?

Chipletz and this kind of context of 3DICs really exploded a couple years ago. People were kind of talking about it. It wasn’t really forefront in the industry like it is now. It’s really taken hold. But at that time, we had a lot of tools that were used in kind of more traditional, at least from an analysis standpoint, right? Across the industry, tools were really catered to traditional packages and PCB architectures.

So one of Chipletz’ early criteria, they said, okay, we’ve got this massive floor plan for this design. Can you even load it in? So can you load it into your analysis tools to even be able to think about running analysis. Not that we need you to run the analysis yet. Can your tools even, do they have the capacity to load in, you know, a 500 or a million pin count design? So initially it was, you know, it was a lot of us working with our R&D teams, you know, getting kind of those capabilities, capacities up. And sure enough, not only were we able to demonstrate, yes, we can handle these architectures.

But let’s start doing this, let’s start doing some real analysis. So we started with kind of the low hanging fruit. Let’s look at our DCIR drop across this thing. Let’s start doing some early PDN analysis. We were kind of able to demonstrate with them not only Siemens tool capabilities, but also our willingness to kind of work with them and attack all these challenging roadblocks.

John Caka (16:05.678)

You know, they were looking for, like I said, mainly it was, can you guys handle this? Can you guys bring this in? Do you have the layout tools to run the layout? Do you have the analysis tools? And fortunately, you know, we were able to check all the boxes and they had a successful tape-out of their initial demonstration vehicle and they’re on to rev two of this design now.

John McMillan (16:35.118)

Wow, that’s great. It’s a great story. Thanks for sharing that. Well, it’s been a great discussion, John. Really appreciate you coming. Any final thoughts before we wrap up this episode?

John Caka (16:38.892)

Absolutely.

John Caka (16:47.958)

Yeah, I think, you know, 3DICs are definitely here to stay. Like I said a few years ago, it was some conference papers. It was, you know, this is the technology that might be around. I think the industry is showing that no, 3DICs are real. They provide an excellent solution to kind of Moore’s law scaling potentially, you know, being able to increase your wafer yield.

Kind of be able to modularize everything is a really fantastic way kind of for the industry and to really lead and drive innovation. So it’s a fantastic time to be a part of this industry and to be associated with Siemens who has such a wide portfolio of being able to attack these problems. Learn every day and be able to help customers like Chipletz have successful designs is the best part of job.

John McMillan (17:53.39)

Awesome. Great. Thanks, John. Appreciate it. Thanks for joining me today and sharing your knowledge and insights.

Yeah, absolutely. Thanks. I’ve learned a lot, a lot of insights and necessity importance for signal integrity and power integrity, particularly in analysis throughout the 3DIC design flow. That’s it for this episode of the 3DIC podcast. To all our listeners and viewers, thank you for joining us today. And be sure to check out the show notes to learn more about today’s topic.

John Caka (17:55.874)

Yep, thank you, John.

John McMillan (18:19.288)

And also be sure to follow this podcast on your YouTube or your favorite streaming service like Spotify. So you don’t miss the next episode of the 3D IC podcast. Thanks, John.

John Caka (18:31.022)

Thanks.