From 2.5D to true 3D IC: What’s driving the next wave of integration.​

3D IC Podcast – 2025 – Kevin Rinebold

John McMillan
Welcome to the Siemens 3D IC podcast series, where we dive into the exciting world of semiconductor chiplet integration and advanced technology platforms using two and a half and 3D techniques. I’m your host, John McMillan. In this podcast series, I talk with industry leaders and subject matter experts to discuss the latest on 3D IC chiplet ecosystems, industry trends, and roadmaps.

In today’s podcast, we’re going to take a deep dive into 3D IC design, and the mindset, and what the next wave of 3D IC integration looks like. I’m excited to welcome my special guest, Kevin Reinbold. He’s the 3D IC packaging and account technology manager and co-design expert here at Siemens EDA.

Welcome, Kevin. It’s great to have you here on the podcast today. And before we dive into today’s discussion, it’d be great if you could share a little bit about yourself, your background, and your current role.

Kevin Rinebold
Yeah. Thanks, John. Thanks for welcoming me and being on the podcast today. I’ve been looking forward to it. So as you can probably tell, I’ve been doing this for a long time. We’ve got 35 years or so into the advanced packaging 3D IC space, primarily in customer-facing roles.

So the benefit of that position allows me to interact with customers very early on, to see what type of technologies that they’re starting to engage on, and basically working with them to make sure we have the appropriate capability in our products and that we’re going to be able to help them to tape out their designs.

John McMillan
Awesome, great. I’m really excited about this conversation. Let’s just jump right in. So we’ve covered 3D IC design best practices all season on this podcast. Where does the industry currently stand?

Kevin Rinebold
Yeah, so it’s interesting, right? I mean, if we kind of separate out the industry to a couple different aspects, if we look at what the hyperscalers are doing, the big data center type folks and the vertically-integrated folks, they’re the ones that are most active.

They’re delivering products in the high-performance compute space, developing AI accelerators. And the commonality there is, most part, they’re developing compute chips or system on chips, and they’re integrating that with memory, high bandwidth memory or HBM on a silicon interposer.

So that seems to be kind of the sweet spot of the market today. If we zoom out a little bit and we look at the broader market, I would say we’re still early stages with an evolving ecosystem. I think a good example of that evolution is in the area of design enablement.

When we talk about design enablement, these are things like the PDKs or process design kits, the tech files, the rule decks necessary to start and verify a design. So if we look at like the silicon foundries, they’ve been doing this for years, right?

They know how to do it, it’s a known process, it’s a known methodology. I think for some of the OSATs, the specialty outsourced assembly and test suppliers and others in the supply chain, I think it’s still a little bit of a learning process.

They’re working with their customers to understand the customer expectations, and the way this manifests itself is we see various levels of design enablement. Right now, most of that’s around the DRC decks, the design rule checking decks necessary to verify design.

I think the other aspect of that is that many in the ecosystem are part of TSMC’s 3DFabric Alliance, which to me feels like a forcing function, right? It’s forcing them to drive this enablement activity and facilitate design exchange.

I think a byproduct of that is that’s really encouraging to see the investment in these suppliers to develop competitive technologies and build out manufacturing capacity. One last point I would also make is in the context of chiplet integration.

I think we’ve all seen some expectation of this kind of mix and match, Lego-based approach, which in my opinion is still a little bit aspirational, but there are encouraging signs, right? We’re seeing an increasing number of design starts using the UCIe interface standard to integrate various chiplets beyond just the memory and compute devices.

And we’re also seeing an increasing number of specialty chiplets from IP providers like Alphawave that I think further helps accelerate the general adoption of chiplets.

John McMillan
Gotcha. You mentioned TSMC 3D, is it really 3D design or is it like two and a half D?

Kevin Rinebold
So as I mentioned at the top of the call, I’m customer facing. I talk to customers all the time, and yeah, they talk about wanting to be able to do 3D IC, but one of the first things I go through with them is a level set exercise, to understand exactly what they’re talking about, because I think in general, from an industry perspective, we use that term 3D IC very broadly to encompass all things advanced packaging.

I would say most of the stuff that we see today is of the two and a half D variety, or it’s a couple of die sitting on a silicon interposer, sitting on an organic substrate. That’s the majority of what we see.

We are starting to see new design starts, though, where we are truly seeing true 3D SOAC integration, where we have two dies sitting on top of one another, and an N2 die or an N3 die stack connected via hybrid bonding.

And then that in itself sits on top of maybe an advanced technology like Silicon Bridge, like TSMC’s CoWoS-L, Intel’s EMIB technology. So we’re starting to see the true implementation of 3D architectures.

John McMillan
Yeah, I know I’ve seen, and I know you obviously have seen customers are really interested in learning more about it, everything they can. I see them consuming content about it. Why aren’t we investing so much in it, and why are customers wanting to be educated so much about it, 3D IC?

Kevin Rinebold
Yeah, so I mean, we’ve been talking about this for a long time collectively, so I think most recognize that Moore’s law is slowing down. There’s an increasing performance gap between what we need from a functional standpoint versus what process node scaling alone cannot deliver, right?

So this is really driving this notion of a systems of chips versus system on a chip. Sometimes, we’ll refer to this more than more. So I think that’s kind of the underlying theme. I also like to talk, though, about the cost and risk aspect of advanced node.

I’m sure many of the listeners have seen the charts talking about the NRE charges for advanced node approaching $500 million or more for like a five-nanometer process. There’s only a limited number of companies that can absorb those types of charges and have the average selling price of their products or the volumes to actually support that.

So I think that’s one of the underlying drivers.

John McMillan
I love getting these customer insights. So in your conversations with customers, what do you see as the tipping point that sends them over to 3D IC design?

Kevin Rinebold
Yeah, so we just talked about the business aspects of it, the cost and risk, right? From a technical aspect, I think first is access and proximity to high bandwidth and memory. Hyperscale, edge compute applications require a lot of low-latency memory.

The designs we see today typically have four to eight HBM stacks. The new design starts that we’re seeing have 16, and I expect that trend to continue upwards. When we go to HBM, though, it requires an interposer-type substrate to support the various bump geometries associated with the HBM technology.

Beyond that, I think we get into things like reticle limits and die size. Overall chip size is limited by the lithography equipment, and then there’s also the yield aspect of fabricating larger chips.

It’s not cost effective to fab a large SOC where many of the IP blocks don’t benefit from the advanced node scaling. IO is a good example of that. I think most recognize that it’s more cost effective to limit advanced nodes to compute cores, fab smaller chips, and then leverage 3D IC to integrate that.

And I think this is indicative of the design starts that we’re seeing. We’re seeing design starts that utilize 3D SOIC stacking to put the compute cores together, attach them using hybrid bonding, and then attach them to the substrate.

So it’s really, it’s about right sizing the process node to the IP.

John McMillan
Gotcha. That sounds really complex for a company to take this on. So are they actually prepared to do designs with two and a half and 3D IC technology?

Kevin Rinebold
Yeah, so one thing I like about this industry, it doesn’t get boring. A week doesn’t go by with some type of announcement, some new substrate technology, some new assembly format. Just thinking recently, things like glass interposers or panel-level processing.

Yeah, so it’s a constant challenge to keep pace with these evolving technologies. And if we look at where the hyperscalers are, they’re clearly leading the way, right? They’re doing the bulk of advanced 3D IC packaging today, but I think they find themselves even having to adapt to the new technology.

I think one of the things that we’re seeing right now is a broad adoption of embedded silicon bridge packaging, moving away from things like CoWoS-S to this embedded silicon bridge, like Intel’s EMIB or TSMC’s CoWoS-L, right?

Those are two prominent examples. When they do that, though, I also think they see new challenges with respect to 3D verification, power delivery, and thermal modeling. And these all necessitate new approaches, new methodologies, new tools.

When we shift gears and think about it from a perspective of a newcomer, it’s an eye-opener, right? First is aligning the application to the technology that meets the performance requirements, that’s cost effective and accessible for volume manufacturing.

Next is dealing with the ecosystem. You have all of these different suppliers, maybe a foundry, maybe an OSAT, maybe some combination of both, and I think they’re going to find various levels of design support, design enablement, and that any of the gaps there, that falls to the customer to resolve.

So there’s this realization that new methods, new tools are needed, and I would say in some cases, maybe even organizational changes need to be considered.

John McMillan
So you mentioned needing these different methodologies. What are some of the methodology changes that are needed?

Kevin Rinebold
Yeah, I think it starts with having a system-centric perspective, starting very early on, where we’re talking about early fore-planning and continuing that all the way through the sign-off stage. Going back to the example we’ve referenced where we have a 3D SOIC stack sitting on some type of silicon bridge, how do we get power to the top die?

Or, if we fast-forward to when the design is completed, how do we know it’s connected correctly? To do that, we need to collectively understand how all of the die, the chiplets, the bridges, the package substrate relate to one another to solve that, how they’re stacked, how they’re placed, what the interface layers are.

But there’s even more to it, right? There’s some interdependencies that we need to balance. A good example of that is balancing thermal considerations against single insertion loss. Where we have thermal is such a huge concern for 3D SOIC, we need to understand the impact of that as early as possible, because there’s other stakeholders that need to have that information.

Not only is it going to drive things like the spacing between the devices, but it’s also going to determine the cooling need for the server, based on the thermal. Is it going to be air-cooled?

If it’s air-cooled, how big of a fan do we need? If it’s going to be liquid-cooled, is it a cold plate or is it going to be immersive cooling? That all comes back to the package and the chip, right? So we need to understand that thermal issue.

But here’s the challenge, so maybe that early thermal feedback indicates we want a space the chips out further from one another, which is okay, that makes sense. Improve the cooling between them, but then doing so can also induce signal insertion loss, because we’re dealing with very long, thin traces that ultimately impacts signal performance.

So we need to figure out what the right balance is. Striking that balance really requires a need for early predictive modeling, taking downstream modeling tools and adapting them for early modeling in what we would call a shift-left methodology.

The idea here is we want to enable fast evaluation of multiple scenarios, allowing the engineer to make educated engineering decisions.

John McMillan
Yeah, that makes sense. So would you say it’s more of a shift in mindset that’s required, then?

Kevin Rinebold
Yeah. I mean, and that’s part of it, right? So we touched on the methodology aspect, but I think there’s also an organizational piece of it. We talked about at the top. I mean, one of the benefits I have is I get to work with a lot of different customers to see what works well, also see what maybe doesn’t work so well sometimes.

I think part of it’s, for so long, the chip, the package system design has been kind of this over-the-wall process with minimal action, minimal interaction between the various design teams. 3D IC really requires a well-integrated, multi-discipline team where we have expertise in single integrity, power integrity, thermal, layout, verification and so on.

And it’s really getting harder to delineate where the chip ends and the package starts. So the over-the-wall, siloed engineering teams, that’s not going to work for 3D SOIC.

John McMillan
Sounds like you’ve see this a lot and you encounter this a lot. So what do you see as Siemens’ role in facilitating this shift?

Kevin Rinebold
Yeah, so I think it starts with the customer understanding what their current needs are, what their future needs are. In many cases, partnering with them to develop high-value solutions. One of the big advantages we have at Siemens is we have a very broad portfolio of technology to draw from.

It’s not just the Calibre product line or the Xpedition product line, but it’s things like IP through our partnership with Alphawave, a lot of new options for multi-physic modeling through our acquisition of Altair all the way through the enterprise data management aspect.

And I think one of the big things that we can bring is being able to bridge the different user personas and really improve and facilitate collaboration across the various engineering teams. I think the example I gave earlier where we allow the electrical engineering person to evaluate thermal aspects through predictive modeling, I think that’s a pretty good example.

We also coordinated with our customers to focus on roadmaps, making sure we have sufficient tool capacity, sufficient tool performance, because as we’ve seen throughout the series, these are very large, complex designs that are going to tax any of the products out there, so being able to stay ahead of the curve.

But it’s more than just having the capacity and performance, it’s also developing the corresponding functionality to address the increasing complexity and scale. things like incorporating hierarchy and physical reuse, introducing new technology to do UCIe protocol compliance, or leveraging AI to help go through all of the various scenarios, helping us come up with the best possible solution that strikes the balance between thermal, electrical, and so on.

And the other thing, but that’s something, sometimes we overlook it, and at least from my perspective, and this is, I think, one of the big advantages we have is, yeah, obviously there’s some product aspect of what we have, but there’s also a lot of expertise and technical depth in our AE organization.

It’s a very valuable asset to our customers, as they try to ramp up new technologies, new methodologies. It’s something that we can deploy that I think our customers are very appreciative of.

John McMillan
Yeah, you’re in a really unique position. You can see where the customers are, where the tools are, and you can see where the technology is going. So knowing all of that, where do you think the industry will be in five years, with all this?

Kevin Rinebold
Yeah, I would expect the evolution, the maturing of standards around chiplet integration, that’s really going to be needed. I mean, if we’re ever going to get to this notion of Lego block, plug-and-play integration, that’s going to have to happen.

And I’m talking more than just interface standards like UCIe, but it’s how the mechanical, the thermal, the reliability of information is distributed. Ultimately, getting to the place where we have this open marketplace or open chiplet marketplace where, as I’m designing, I can select a chiplet, pull up all my sourcing information, pull that model into my design, similar to what we do in the system space with our supply frame products, so I think that’s one.

And I think the designs are going to continue to scale. They’re going to get bigger, they’re going to get more complex, more HBM. I don’t see that trend changing. What’s interesting now is we’re seeing some new technology where the entire wafer itself becomes the system.

So system on wafer, where we have these large, 300-millimeter systems with multiple chiplets on them, I think we’re going to start to see more of that. I’m hopeful that we will see advances in organic substrates in place of silicon interposers.

There’s some early indications that there’s technologies out there that can provide comparable feature sizes, but at a much lower price point. And I think ultimately we’re going to continue to have the discussion around power and thermal.

That’s going to be a continuing challenge. How do we get the power into the 3D IC stack and how do we get the heat out?

John McMillan
Well, this has been a great discussion, Kevin. I really appreciate your time. Do you have any final thoughts before we close out this episode?

Kevin Rinebold
No, I think this has been a great discussion. I’ve enjoyed the series that you guys have done, and I hope everybody else finds this as informative as I have. So thanks, John.

John McMillan
Yeah, great. Thanks very much, and thanks for joining me today, sharing your knowledge, insights, and all about the importance of 3D design today, the mindset, what the next wave with 3D IC integration looks like. That’s it for this episode of the 3D IC podcast. To all our listeners and viewers, thanks for joining us today.

And be sure to check out the show notes to learn more about today’s topic, and also be sure to follow the podcast on YouTube or your favorite streaming service so you don’t miss any episodes of the 3D IC podcast. Thanks again, Kevin.

Kevin Rinebold
Thank you.