How can IC and package designers navigate the complexities of heterogeneous integration?
Heterogeneous integration has transformed the design of complex devices, enabling engineers to swiftly and affordably create advanced system-in-packages by combining third-party IPs into chiplets. This technology offers advantages such as enhanced performance, power efficiency, scalability, flexibility, and cost-effectiveness.
But the shift to 2.5D/3DIC is far from straightforward. Existing design tools and methodologies were originally designed for monolithic devices, concentrating on individual device levels. As such, they are often incapable of maximizing the possibilities of chiplet integration.
Heterogeneous integration necessitates a shift to system-level technology co-optimization (STCO): IC and package designers simply cannot avoid considerations of power, performance, area, cost, and reliability across various components, including silicon, package, interposer, and PCB. A single decision on one level has a domino effect on all others.
Today’s tools and methodologies must support such complex decision making.
Define millions of bump connection – with a spreadsheet?
Take for example the challenge of net list definition. When designing a system, each component introduced needs to be connected to the others. Designs with hundreds of thousands of connections are now common, and hybrid bonding technology is promising even more connections.
These connections are typically handled using spreadsheets, each connection defined individually, which is tedious and prone to errors. This is especially challenging with technologies like HBM that have wide connectivity.
Spreadsheet-based solutions, even with custom macro development, do not scale to hundreds of thousands or millions of bumps.
So, substrate designers are now turning to language-based design methods to tackle the complexity of system connectivity. Using Verilog RTL with proper bus notation proves to be more efficient and less error-prone compared to manually defining connections one by one in a spreadsheet or developing custom Excel macros for connectivity tables.
In actuality, the role of designers is shifting towards system integration tasks. Designers now need to collaborate with various stakeholders who are simultaneously developing their content while the package or interposer is being designed. This collaboration aims to create a design that is both electrically and physically accurate and operates as intended.
Build the 3D IC digital twin in an integrated environment
It’s no longer enough for tools to handle specific tasks, such as the abovementioned net list definition, even if they do those really well. IC package designers need work environments that support and bolster integration with parallel domains, which will all make their way into the final system.
In the newly released eBook by Keith Felton, IC Packaging product marketing manager, Integrating chiplets into an advanced packaging platform: Building the design, we tackle the challenges of heterogeneous integration, focusing on the first stage: building the 3D digital twin. Download it now to learn more about methodologies and tools that empower design engineers to manage and communicate heterogeneous data across enterprise-wide teams while maintaining digital continuity.
