Interconnect Robustness Depends on Scaling for Reliability Analysis

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness…

Efficient Parasitic Extraction Techniques for Full-Chip Verification

By Yousry Elmaghraby, Mentor Graphics Choosing the best PEX method for your full-chip or SoC…

Parasitic Extraction for Accurate Signal Integrity Analysis at Advanced Nodes

By Karen Chow, Mentor Graphics Signal integrity analysis at advanced nodes requires new and enhanced…

Parasitic extraction for touchscreen designs

By Mohamed ElRefaee, Mentor Graphics Accurate parasitic extraction of touchscreens is essential for ensuring the…

Extraction Challenges Grow in Advanced Nanometer IC Design

By Carey Robertson, Mentor Graphics The Calibre xACT platform is a new type of extraction…

Parasitic Extraction of FinFET-based Memory Cells

By Karen Chow, Mentor Graphics Accurate and efficient FinFET characterization requires a parasitic extraction tool…

Are multi-patterning corners for parasitic extraction really necessary for 16/14 nm?

By Karen Chow, Mentor Graphics How does multi-patterning impact parasitic extraction? How many corners do…