DAC in December?? A Review of Calibre Design Solutions at DAC 2021

Did it feel a bit weird to be submitting research papers for DAC 2022 while packing to go to DAC…

Interconnect Robustness Depends on Scaling for Reliability Analysis

Interconnect Robustness Depends on Scaling for Reliability Analysis

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…

Efficient Parasitic Extraction Techniques for Full-Chip Verification

Efficient Parasitic Extraction Techniques for Full-Chip Verification

By Yousry Elmaghraby, Mentor Graphics Choosing the best PEX method for your full-chip or SoC design is essential. But how…

Parasitic Extraction for Accurate Signal Integrity Analysis at Advanced Nodes

Parasitic Extraction for Accurate Signal Integrity Analysis at Advanced Nodes

By Karen Chow, Mentor Graphics Signal integrity analysis at advanced nodes requires new and enhanced parasitic extraction techniques

Parasitic extraction for touchscreen designs

Parasitic extraction for touchscreen designs

By Mohamed ElRefaee, Mentor Graphics Accurate parasitic extraction of touchscreens is essential for ensuring the high-quality performance the market demands

Extraction Challenges Grow in Advanced Nanometer IC Design

Extraction Challenges Grow in Advanced Nanometer IC Design

By Carey Robertson, Mentor Graphics The Calibre xACT platform is a new type of extraction tool that provides a range…

Parasitic Extraction of FinFET-based Memory Cells

Parasitic Extraction of FinFET-based Memory Cells

By Karen Chow, Mentor Graphics Accurate and efficient FinFET characterization requires a parasitic extraction tool that can apply different extraction…

Are multi-patterning corners for parasitic extraction really necessary for 16/14 nm?

Are multi-patterning corners for parasitic extraction really necessary for 16/14 nm?

By Karen Chow, Mentor Graphics How does multi-patterning impact parasitic extraction? How many corners do you really need?