Learn how to quickly and easily scan multiple layers of Calibre OPC simulation results in the Calibre RVE tool for…
By David Abercrombie, Rehab Ali, Ahmed Hamed-Fatehy, and Shetha Nolke How the SID-SADP process affects your design decisions –
By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid FEOL CMP modeling helps designers and foundries predict CMP hotspots in advanced…
Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help
By Matthew Hogan, Mentor Graphics Latch-up detection is challenging. Learn how automated LUP checks help you find and eliminate LUP…
By Yousry Elmaghraby, Mentor Graphics Choosing the best PEX method for your full-chip or SoC design is essential. But how…
By David Abercrombie and Alex Pearson, Mentor Graphics Applying ECOs to multipatterned designs can be a nightmare, unless you plan…
By David Abercrombie, Mentor Graphics How do you know which double patterning flow to use?
