Fixing DRC errors in SADP designs at sign-off—Nobody said it was easy (but it can be easier…and much faster)

Fixing DRC errors in SADP designs at sign-off—Nobody said it was easy (but it can be easier…and much faster)

By David Abercrombie – Mentor, A Siemens Business SADP + DRC = headaches? Not any longer.  GLOBALFOUNDRIES and Mentor collaborated…

A look at what’s to come at OIP (hint: we’ll be there!)

A look at what’s to come at OIP (hint: we’ll be there!)

The 2018 TSMC Open Innovation Platform® (OIP) Ecosystem Forum in Santa Clara starts this Wednesday, October 3rd! As usual, Mentor…

Fractures aren’t always a bad thing…especially in resistance extraction

Fractures aren’t always a bad thing…especially in resistance extraction

By Hossam Sarhan – Mentor, A Siemens Business Did you know? IC designs that use unconventional metal structures with multiple…

A brief history of the process design kit

A brief history of the process design kit

By John Ferguson – Mentor, A Siemens Business Do you really know what goes into a PDK? You might be…

Get rid of pesky parasitics fast!

Get rid of pesky parasitics fast!

By Karen Chow and Claudia Relyea – Mentor, A Siemens Business Parasitics hampering the performance of your advanced node or…

Do you trust your reliability baseline? Well, do you?

Do you trust your reliability baseline? Well, do you?

By Matthew Hogan – Mentor, A Siemens Business Custom reliability verification? No reliability verification? Foundry-qualified reliability rule decks provide an…

Did you know the Calibre PERC platform has an automated waivers functionality?

Did you know the Calibre PERC platform has an automated waivers functionality?

By Dina Medhat – Mentor, A Siemens Business   Want to waive complex reliability conditions? Manage multiple users waiving results…

P&R Designers—Want to quickly analyze and debug signoff DRC errors in P&R?

P&R Designers—Want to quickly analyze and debug signoff DRC errors in P&R?

By Srinivas Velivala – Mentor, A Siemens Business Want a better, faster way to debug signoff DRC errors in P&R?…

Pssst, digital designers…wanna save WEEKS on your tapeouts?

Pssst, digital designers…wanna save WEEKS on your tapeouts?

By Srinivas Velivala – Mentor, A Siemens Business Who doesn’t want to save weeks of precious time on their tapeouts…