Lane ends—full-chip merge ahead

By James Paris – Mentor, A Siemens Business

Fast layout merging during continuous build flows makes it easier to solve all design issues early and accurately. Here’s a few things you should consider when optimizing your parallel design implementation flows…

Merging into traffic at speed is one of the scariest skills a new driver must learn. Too slow, and you run the risk of collision. Too fast, and you might not have time to see that vehicle trying to merge from the other lane. Once learned, however, merging is a skill that lets a myriad of vehicles share the road while reaching their destinations in a timely and efficient manner.

Database merging is a similar skill that provides similar benefits. Most design teams run full-chip verification on SoC designs multiple times during design implementation. However, that means collecting the latest physical layout data of multiple elements in various stages of progress, and merging them into a single OASIS or GDSII database for the full-chip verification run. Establishing a data merging flow that takes all the needs of the continuous build parallel design implementation flow into consideration requires some attention to detail and careful planning.

To help you out, our white paper, Fast layout merging for continuous build design flows, points out some of the potential roadblocks, and introduces you to strategies and tools you can use to avoid them. Learning how to create a fast, comprehensive database merging solution is a skill that will help speed you (and your company) on your way to market success.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/calibre/2019/01/21/lane-ends-full-chip-merge-ahead/