Design and verification flows are multifaceted and predominantly built by bringing tools and technology together from multiple sources. The tools…
I have always been wanting to contribute to the growing verification engineering community in India, which Mentor’s CEO Wally Rhines…
Accellera Handoffs UVM to IEEE It has been a long path from Mentor’s AVM to IEEE P1800.2. But the moment…
If you were not one of the 100’s of visitors to the Verification Academy booth at DAC 2015 and missed…
ASIC/IC Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the 2014…
FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2014 Wilson…
Still having fun doing UVM and Class based debug? Maybe a debug contest will help. I had a contest with…
In a recent post on deepchip.com John Cooley wrote about “Who Knew VIP?”. In addition, Mark Olen wrote about this…
With a name like “Fitzpatrick,” you knew I’d be celebrating today, right? Well, there’s no better way to celebrate this…
