UVM Forum 2015 LIVE!

UVM Forum 2015 LIVE!

Verification Academy Brings “UVM Live” to the Santa Clara Convention Center For everyone involved in the functional verification of electronic…

IEEE-SA EDA & IP Interoperability Symposium

IEEE-SA EDA & IP Interoperability Symposium

Design and verification flows are multifaceted and predominantly built by bringing tools and technology together from multiple sources.   The tools…

Ready for a Verification Extravaganza in the Land of Verification Engineers?

Ready for a Verification Extravaganza in the Land of Verification Engineers?

I have always been wanting to contribute to the growing verification engineering community in India, which Mentor’s CEO Wally Rhines…

UVM: The Next IEEE Standard (1800.2)

UVM: The Next IEEE Standard (1800.2)

Accellera Handoffs UVM to IEEE It has been a long path from Mentor’s AVM to IEEE P1800.2.  But the moment…

Verification Horizons: The DAC 2015 Issue

Verification Horizons: The DAC 2015 Issue

If you were not one of the 100’s of visitors to the Verification Academy booth at DAC 2015 and missed…

Part 10: The 2014 Wilson Research Group Functional Verification Study

Part 10: The 2014 Wilson Research Group Functional Verification Study

ASIC/IC Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the 2014…

Part 6: The 2014 Wilson Research Group Functional Verification Study

Part 6: The 2014 Wilson Research Group Functional Verification Study

FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2014 Wilson…

UVM Debug. A contest using class based testbench debug…

UVM Debug. A contest using class based testbench debug…

Still having fun doing UVM and Class based debug? Maybe a debug contest will help. I had a contest with…

No to Know VIP

No to Know VIP

In a recent post on deepchip.com John Cooley wrote about “Who Knew VIP?”. In addition, Mark Olen wrote about this…