As I mentioned in my last UVM post, UVM allows engineers to create modular, reusable, randomized self-checking testbenches. In that…
Having been deeply involved with Universal Verification Methodology (UVM) from its inception, and before that, with OVM from its secret-meetings-in-a-hidden-hotel-room…
Where might our paths cross? It is always challenge to fit all the needed visits in during the Design Automation…
IEEE Std. 1666™-2011 Available as Free Download In November 2011 I blogged the IEEE Standards Association (SA) approved a revision…
IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced…
System Standards Worlds Initiate Unification Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC…
Open SystemC Initiative Tackles the Future If you have examined the DVCon program, you know that it is a week…
You Are Invited – Register Now! (seating is limited) Sunday, June 13 2:30pm – 6:00pm Anaheim Hilton, California Ballroom A…
Noted EDA analyst and guru Gary Smith delivered keynote address: “ESL: Where We Are and Where We’re Going” OSCI sponsored…
