Accellera Handoffs UVM to IEEE It has been a long path from Mentor’s AVM to IEEE P1800.2. But the moment…
If you were not one of the 100’s of visitors to the Verification Academy booth at DAC 2015 and missed…
ASIC/IC Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the 2014…
Learn more about DDA at DAC At DAC – Mentor Graphics and Cadence Design Systems are coming together to usher…
FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2014 Wilson…
Still having fun doing UVM and Class based debug? Maybe a debug contest will help. I had a contest with…
It is always good to pause to recognize the companies and individuals with whom we collaborate to create the verification…
Accellera Approves Creation of Portable Stimulus Working Group At DVCon 2014, Mentor Graphics proposed Accellera launch an exploratory exercise, called…
SystemVerilog Testbench Debug – Are we having fun yet? Fun Debug should be fun. Watching waveforms march by, seeing ERRORS…
