Supporting A Season of Learning

Supporting A Season of Learning

From those just beginning to study electronic systems design to the practicing engineer, this is the time of the year…

DVCon Goes Global!

DVCon Goes Global!

The ever popular Accellera Design & Verification Conference held annually in Silicon Valley is going global.  Accellera System Initiative has…

Accellera Approves UVM 1.2

Accellera Approves UVM 1.2

Accellera has announced the completion of a multi-year effort to update its latest edition of the Universal Verification Methodology (UVM). …

Mentor Enterprise Verification Platform Debuts

Mentor Enterprise Verification Platform Debuts

Its always fun to take the wraps off of solutions we have been hard at work developing.  The global team…

DVCon 2014: Standards on Display

DVCon 2014: Standards on Display

One of the nice things about DVCon is the update one can get from the developers of IEEE and Accellera…

Managing Verification Coverage Information

Managing Verification Coverage Information

The UCIS Story There is no secret as design sizes grow it is doubly burdensome for verification.  Two factors that…

IEEE Standards Association Symposium on EDA Interoperability

IEEE Standards Association Symposium on EDA Interoperability

Low Power Flow Kicks-off Symposium In the world of electronic design automation, as an idea takes hold and works its…

Part 8: The 2012 Wilson Research Group Functional Verification Study

Part 8: The 2012 Wilson Research Group Functional Verification Study

Language and Library Trends This blog is a continuation of a series of blogs that present the highlights from the…

A Short Class on SystemVerilog Classes

A Short Class on SystemVerilog Classes

It is often said that the English language is one of the most difficult languages to learn: inconsistent spelling rules;…