Simulation

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Accellera announces fee-free availability of IEEE Std. 1801™-2024

March 19, 2025

Accellera announced the latest revision of the IEEE Standard for Design and Verification of Low-Power Energy-Aware Electronic Systems, also known…

By Dennis Brophy
3 MIN READ

GOMACTech 2025 Preview: Improving Productivity with Parallel Simulation (Poster P.9)

March 10, 2025

Field Programmable Gate Arrays (FPGAs) continue to be a critical part of system designs, and their complexity grows as new…

By Joe Hupcey III
2 MIN READ
Backpacking Yosemite Aug 2024

Got Coverage?

February 14, 2025

Welcome to 2025. What happened?! “Coverage” in August in Yosemite backpacking has a different meaning. In August? Snow? Lots of…

By Rich Edelman
3 MIN READ

Breaking the Bottleneck: A Smarter Approach to Semiconductor Verification

February 5, 2025

The semiconductor industry is facing a new reality: traditional verification methods can no longer keep pace with the rapid evolution…

By Harry Foster
< 1 MIN READ

Unlocking the Future of High Bandwidth Memory with Siemens and Rambus

November 5, 2024

In a recent webinar, Siemens partnered with Rambus to delve into the transformative world of High Bandwidth Memory (HBM), focusing…

By Dennis Brophy
2 MIN READ

Exploring essential concepts in Formal Verification

September 18, 2024

What is a witness? is it the same as a counterexample? A witness is a sequence of inputs that demonstrates…

By Nicolae Tusinschi
3 MIN READ

Siemens EDA at DVCon India 2024: Join Us for an Exciting Lineup!

September 5, 2024

We are thrilled to announce Siemens EDA’s participation in DVCon India 2024, taking place on September 18-19 at the Radisson Blu in Marathahalli, Bangalore. This year’s event promises to be a hub of innovation and knowledge-sharing, and we are excited to be a part of it.

Siemens EDA will be showcasing a range of informative sessions and exhibits designed to help you engineer a smarter future faster.

By Dennis Brophy
2 MIN READ

Jump-Start Your UVM Journey with UVM Framework (UVMF)

September 4, 2024

Bob Oden shares insights on how the Universal Verification Methodology Framework (UVMF) is revolutionizing the verification landscape. UVMF is an advanced toolset that…

By Dennis Brophy
2 MIN READ
Simulation is Key in design verification process

The importance of simulation in the pursuit of absolute speed!

April 2, 2024

A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process

By Sunil Sahoo
3 MIN READ