Part 5: The 2012 Wilson Research Group Functional Verification Study

Part 5: The 2012 Wilson Research Group Functional Verification Study

  Effort Spent in Verification This blog is a continuation of a series of blogs that present the highlights from…

Part 4: The 2012 Wilson Research Group Functional Verification Study

Part 4: The 2012 Wilson Research Group Functional Verification Study

Reuse Trends This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson…

Part 3: The 2012 Wilson Research Group Functional Verification Study

Part 3: The 2012 Wilson Research Group Functional Verification Study

Clocking and Power Trends In Part 2 of this series of blogs, I continued the discussion focused on design trends…

Part 2: The 2012 Wilson Research Group Functional Verification Study

Part 2: The 2012 Wilson Research Group Functional Verification Study

Design Trends (Continued) In Part 1 of this series of blogs, I focused on design trends (click here) as identified…

Part 1: The 2012 Wilson Research Group Functional Verification Study

Part 1: The 2012 Wilson Research Group Functional Verification Study

 Design Trends In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of…

What’s the deal with those wire’s and reg’s in Verilog

What’s the deal with those wire’s and reg’s in Verilog

A unique concept most beginners have trouble grasping about the Verilog, and now the SystemVerilog, Hardware Description Language (HDL) is…

Prologue: The 2012 Wilson Research Group Functional Verification Study

Prologue: The 2012 Wilson Research Group Functional Verification Study

This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional…

Improving simulation results with formal-based technology

Improving simulation results with formal-based technology

When it comes to formal methods, many engineers are skeptics. Perhaps this is due to value propositions that have been…

Virtual Emulation for Debugging

Virtual Emulation for Debugging

A system-level verification engineer once told me that his company consumes over 50% of its emulation capacity debugging failures. According…