formal verification

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BUGGED OUT PODCAST

Introducing BUGGED OUT — A new bite-sized podcast for verification engineers

November 10, 2025

BUGGED OUT Podcast

By Harry Foster
2 MIN READ
Functional Verification Insights with Abhi Kolpekwar

Functional verification insights: a conversation with Abhi Kolpekwar

September 15, 2025

Over the years, I’ve had the privilege of sharing industry data and analysis through the Siemens EDA & Wilson Research Group…

By Harry Foster
2 MIN READ

GOMACTech 2025 Preview: FPGA Safety and Security Policy Compliance via HDL-to-Bitstream Equivalence Checking (Session 43.5)

March 4, 2025

Security and safety policies across domains such as embedded security, defense safety, and automotive safety have been updated to require…

By Joe Hupcey III
3 MIN READ

DVCon 2025: A must for hardware design and verification engineers

February 12, 2025

I’ve attended every DVCon US conference since its inception, over 30 years ago. I’ve also given keynotes at DVCon India….

By Dave Rich
2 MIN READ

Breaking the Bottleneck: A Smarter Approach to Semiconductor Verification

February 5, 2025

The semiconductor industry is facing a new reality: traditional verification methods can no longer keep pace with the rapid evolution…

By Harry Foster
< 1 MIN READ
osmosis 2024

osmosis 2024 – pushing the boundaries of formal verification

December 11, 2024

Thank you for making osmosis 2024 a success! The annual osmosis 2024 event has once again proved to be a…

By Nicolae Tusinschi
< 1 MIN READ
osmosis 2024

The osmosis formal verification conference celebrates its 5th anniversary this October 17!

September 26, 2024

Calling all formal verification enthusiasts: We are excited to invite you to osmosis 2024, marking the 5th anniversary of this…

By Joe Hupcey III
2 MIN READ

Exploring essential concepts in Formal Verification

September 18, 2024

What is a witness? is it the same as a counterexample? A witness is a sequence of inputs that demonstrates…

By Nicolae Tusinschi
3 MIN READ

Assertions and benefits of abstractions in Formal Verification

September 11, 2024

How are assertions specified? Assertions are typically specified using languages like SystemVerilog Assertions (SVA) or Property Specification Language (PSL). These…

By Nicolae Tusinschi
3 MIN READ