More DVCon–More Mentor Tutorials!

More DVCon–More Mentor Tutorials!

As DVCon expands, we at Mentor Graphics have grown our sponsored sessions as well.  Would you expect less? In DVCon’s…

UVM 1.2: Open Public Review

UVM 1.2: Open Public Review

UVM 1.2 Release is Imminent As vice chair of DVCon 2014, I can share with you that the Universal Verification…

DVCon 2014: Standards on Display

DVCon 2014: Standards on Display

One of the nice things about DVCon is the update one can get from the developers of IEEE and Accellera…

IEEE Approves New Low Power Standard

IEEE Approves New Low Power Standard

IEEE 1801™-2013 Enters Pre-Publish Phase The completion and approval of electronic design automation standards has seemed to be the order…

IEEE Approves Revised SystemVerilog Standard

IEEE Approves Revised SystemVerilog Standard

IEEE Std. 1800™-2012 Officially Ratified The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft…

Verification Standards Take Another Step Forward

Verification Standards Take Another Step Forward

Accellera Ushers in Unified Coverage Interoperability Standard (UCIS) For the past few months, Accellera’s Unified Coverage Interoperability Standards working group…

Introducing UVM Connect

Introducing UVM Connect

In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should…

UVM: Some Thoughts Before DVCon

UVM: Some Thoughts Before DVCon

It is time to talk about what happens next with UVM The Design and Verification Conference (DVCon) has become the…

Language Transitions: The Dawning of Age of Aquarius

Language Transitions: The Dawning of Age of Aquarius

Wally Rhines DVCon 2011 Keynote Highlights Survey on Verification Languages OK, maybe it is not the Dawning of the Age…