The Grapes Are Ready

The Grapes Are Back! And Cake! And C Tests with UVM and Transactions For All! Easy.

The grapes have returned – this weekend was “harvest” time. Jelly everywhere. A lot like this year here at Siemens….

Industrial-Grade AI in EDA: From Promise to Practice — A Siemens Panel at DAC 2025

Industrial-Grade AI in EDA

Backpacking Yosemite Aug 2024

Got Coverage?

Welcome to 2025. What happened?! “Coverage” in August in Yosemite backpacking has a different meaning. In August? Snow? Lots of…

Simulation is Key in design verification process

The importance of simulation in the pursuit of absolute speed!

A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process

UVM Objections at DVCON US 2024 – and Grape Jelly

Boiling Grape Jelly Stay with me – trust me. There’s a tie in to UVM Objections and DVCON US 2024….

To UVM Config or Not at DVCON US – Can chatGPT do it better?

It’s all about speed and productivity for Verification Engineers and Designers. And of course, the UVM is the ticket, and…

My Day At The Beach - Early

UVM Testbench Debug – A Day At The Beach – Right?

Some people think UVM Testbench Debug is a drag. But really, it depends. I think it’s a day at the…

Finding Data

Finding Data Another weekend of weeding. Dark Star – Ceanothus – A California Lilac in the picture. (Not a weed)….

Verilog & VHDL Debug & Weeding

A short exploration through using better debugging tools for better productivity.