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The Walking LRM

The Walking LRM

My last blog post was written a few years ago before attending a conference when I was reminiscing about the…

Will UVM 1800.2 Leave You Behind?

Will UVM 1800.2 Leave You Behind?

We recently reached yet another important milestone in the life of the Universal Verification Methodology. The IEEE 1800.2 UVM Standard…

How Any Verification Engineer Can Quickly Create a Complex Testbench

How Any Verification Engineer Can Quickly Create a Complex Testbench

Over the past decade or so, the state of the art in design verification has taken a huge leap forward…

How To Connect Your Testbench to Your Low Power UPF Models

How To Connect Your Testbench to Your Low Power UPF Models

Face facts: power supply nets are now effectively functional nets, but they are typically not defined in the design’s RTL….

Holiday UVM Register Indigestion

Holiday UVM Register Indigestion

Happy Holidays! Hopefully, wherever you are you are enjoying some time off. At our house, we’re planning a large dinner,…

Conclusion: The 2016 Wilson Research Group Functional Verification Study

Conclusion: The 2016 Wilson Research Group Functional Verification Study

Deeper Dive into First Silicon Success and Safety Critical Designs This blog is a continuation of a series of blogs…

DVCon U.S. 2017: Bigger and Better!

DVCon U.S. 2017: Bigger and Better!

Technical Program is Live For the past several months, the DVCon U.S. Steering Committee has been meeting to craft a…

Emulation and simulation; invaluable tools for IC verification

Emulation and simulation; invaluable tools for IC verification

Emulation technology has been around for a long time—more than four decades by my count—and industry observers believe more than…

Part 12: The 2016 Wilson Research Group Functional Verification Study

Part 12: The 2016 Wilson Research Group Functional Verification Study

ASIC/IC Verification Results This blog is a continuation of a series of blogs related to the 2016 Wilson Research Group…