Thought Leadership

Holiday UVM Register Indigestion

By Rich Edelman

Happy Holidays!

Hopefully, wherever you are you are enjoying some time off. our house, we’re planning a large dinner, including Prime Rib, mashed potatoes and gravy, sweet potatoes, green beans, butternut squash, Brussels sprouts, salad and some delicious Parker rolls. Who knows what else? And of course, pies for dessert. Probably indigestion.

Check out Martha Stewart’s Prime Rib

This great bounty of food is one thing our family looks forward to at this time of year. Some good eats and good time together.

Another great bounty that you might be looking forward to is the UVM Register package. It’s been around since the beginnings of the UVM, 6 years ago, but it’s getting a lot more interest recently. We’re seeing increases in questions, and we’re spending more time helping customers build out their UVM Register verification infrastructure.

But many of the customers aren’t quite sure what to do with the UVM Register package. What do I do about my quirky register models? What kind of coverage do I need? Do I really need to know that all the bits toggled in a system-level simulation? Callbacks? Do I really have to write all that code? I have a special address map – how do I model that? What about memory? No answers here, just a word of caution. Avoid indigestion.

The UVM Register package is big. It weighs in at about a quarter of the UVM.

The uvm-1.2 register source code is 26 files, 21,668 lines, 450 functions, 154 tasks, 48 classes. About 28% of the total lines.

The UVM Register model is sophisticated.

In the UVM 1.2 User Guide, the register documentation is the largest chapter at 50 pages out of 190 total. (Not to mention the almost 200 pages in the UVM 1.2 Class Reference manual out of 938 pages total).

Modeling a 32 bit register with a collection of classes is a lot of overhead.

For a small block it works fine. For a larger block it can become problematic. For a system, it is a real problem – a very large memory footprint for
register modeling.

I’m sure you must have questions too. How do you use the UVM Register package to solve your verification issues? Do you do some things at block level and other things at the system level?

It’s been about 10 years since the AVM came on the scene, followed by OVM and UVM. I’m hoping we can continue innovating, but without the indigestion of code bloat.

 AVM-3.0  :  38 files,  6,598 lines,   275 functions,  24 tasks, 135 classes
 OVM-2.1.2: 106 files, 37,786 lines, 1,230 functions, 159 tasks, 275 classes
 UVM-1.1d : 133 files, 67,965 lines, 1,893 functions, 318 tasks, 375 classes
 UVM-1.2  : 145 files, 75,642 lines, 2,203 functions, 318 tasks, 411 classes

The UVM Register package is big and interesting, just like my Prime Rib dinner. I have a plan to avoid indigestion. Do you?

How are you using the UVM Register package? And how do you avoid indigestion?

Thanks and Happy Holidays


One thought about “Holiday UVM Register Indigestion
  • The concept of RISC was discovered in the 1970s, and great value was found in having a simple, regular register map. I observe that since the 1990s there has been no reason to have CISC-type register maps on components. The solution isn’t to make the tools as complicated as possible to support every possible register map an engineer can build – the solution is to have simple, standard register maps that are easily comprehended, used and verified.

    My biggest design had over 4,000 32-bit registers – it’s not hard if you don’t make your life hard.

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This article first appeared on the Siemens Digital Industries Software blog at