[Preface: at the upcoming DVCon 2018 in San Jose, poster 4.12 addresses some of the issues raised below, as well…
We hope to see you at DVCon U.S. 2018. Mentor will showcase 17 papers and posters during the conference on…
Modern complex chips necessarily have modern complex testbenches. The testbenches of old – wiggling one pin at a time and…
The latest revision to the SystemVerilog standard, IEEE 1800™-2017 was approved at the December 2017 IEEE Standards Association meeting series. …
Our special year-end issue of the Verification Horizons Newsletter (for which this blog is named, by the way) is now available!…
Whether developing tests for software or hardware, test development seems to follow a pretty predictable process: learn about the thing…
In formal verification, proving all of your properties is pretty much the main goal of the whole exercise – if…
No one ever said that functional verification was easy. In fact, from a computer science theoretical perspective verification is considered…
Accellera Systems Initiative recently closed its public comment review period for the Portable Test and Stimulus Standard Early Adopter (EA)…
