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FMCAD 2019: The Most Important Formal Verification Conference You’ve Never Heard Of

FMCAD 2019: The Most Important Formal Verification Conference You’ve Never Heard Of

[Preface: I briefly interrupt my series on The Many Flavors of Equivalence Checking to share this report on an important…

Automotive IC Design Workshop

Automotive IC Design Workshop

Join us Thursday, November 21, 2019 at our offices in Fremont, CA for the Mentor and TowerJazz Automotive Workshop. Register…

The UVM : Is it Safe?

The UVM : Is it Safe?

Is It Safe? It depends. What is the context? Economy? Geo-political situation? Teenage drivers? UVM? I don’t know. Do you…

Questa VRM is the New MS Project

Questa VRM is the New MS Project

I’ve written extensively about agile development from the point of a verification engineer. From the beginning, I’ve been firmly of…

Safety-Critical Design

Safety-Critical Design

Mentor Joins Arm® Functional Safety Ecosystem Mentor is pleased to join the Arm Functional Safety Partner program to bring our…

Don’t Miss the Upcoming DVClub Austin Event!

Don’t Miss the Upcoming DVClub Austin Event!

If you have a passion for design and verification, then I highly recommend that you check out the DVClub. The…

Formal Verification Done Fast

Formal Verification Done Fast

It’s not too late to register for our two-part webinar on faster formal verification. This week and next we will…

Portable Stimulus: Are you Ready for a Verification Revolution?

Portable Stimulus: Are you Ready for a Verification Revolution?

Depending on the revolution and who you happen to be within it, revolution is a risk to avoid at all…

A Little Verilog Knowledge Goes A Long Way in Understanding How SystemVerilog Constraints Work

A Little Verilog Knowledge Goes A Long Way in Understanding How SystemVerilog Constraints Work

In its simplest form, a constraint is nothing more than a Boolean expression with random variables where the solver is…