New RTL Modeling Constructs in Verilog

I’ve been packing up my office as Siemens is closing my location. This marks the longest I’ve ever spent in a single office, a whopping 15 years. Coincidentally, I was in the same building earlier with another company, Avant! for an additional 2 years. I’ve got a box of stuff from previous jobs that I rarely unpack. But it happened to go through it and found the proceedings from what was to become the first DVCon in 1992. I doubt these proceedings exist anywhere in digital form.

In the proceedings was a paper I published about a new RTL modeling construct I added to Verilog before it became an IEEE standard. It eventually became known as a NonBlocking Assignment (NBA).

The Grapes Are Ready

The Grapes Are Back! And Cake! And C Tests with UVM and Transactions For All! Easy.

The grapes have returned – this weekend was “harvest” time. Jelly everywhere. A lot like this year here at Siemens….

First-Silicon Success

Why First-Silicon Success Is Getting Harder for System Companies

First-silicon success is getting harder.

Everyone wants their own chip. Few are hitting first-silicon success.

That’s the paradox shaping today’s semiconductor landscape.

In the 2024 Siemens EDA / Wilson Research Group Functional Verification Study, which I authored, we found that only 14% of ASIC/SoC projects achieved first-silicon success — the lowest figure in more than twenty years of tracking this data.

DVCon India 2025 - 10th Anniversary

Siemens at DVCon India 2025: Driving the Future of Design and Verification

DVCon India 2025, taking place on September 10–11 at the Radisson Blu, Marathahalli, Bengaluru, will mark a special milestone—its 10th anniversary. Over the past decade, DVCon India has grown into one of the region’s most influential conferences for design and verification professionals. Siemens will be prominently featured across vision talks, technical papers, posters, and workshops, showcasing its leadership in AI-driven EDA, hardware-assisted verification, and formal methodologies.

Reminder: DVCon U.S. 2026 Call for Papers – Sept 7th Deadline Approaching!

The DVCon U.S. 2026 Call for Papers deadline is Sunday, September 7th at 11:59 PM. Don’t miss your chance to share your expertise…

Siemens EDA at FMS 2025 – Shaping the Future of Memory and Storage

We’re excited to connect with fellow innovators, engineers, and industry leaders at FMS 2025. Whether you’re attending our sessions or stopping by Booth #1140, we look forward to sharing the latest technical advancements in verification IP, system-level validation, and memory and interconnect technologies.

Questa One Functional Safety

Accelerated Safety Assurance with Questa One Functional Safety Solution

Explore how the Questa One Functional Safety Solution delivers accelerated safety assurance

User2User

Closing the Gap in Software Skills for Verification Engineers

I’m excited to announce next month’s U2U (User-to-User) meeting, followed by a crucial technical training session that no hardware verification…

DVCon 2025: A must for hardware design and verification engineers

I’ve attended every DVCon US conference since its inception, over 30 years ago. I’ve also given keynotes at DVCon India….