Celebrating the Approval of Portable Test and Stimulus Standard (PSS) 3.0

Accellera Systems Initiative has recently announced the approval of the Portable Test and Stimulus Standard (PSS) 3.0, marking a significant milestone in…

Transforming AI with HBM: Siemens’ Avery VIP powers Rambus’ Industry-First HBM4 Memory Controller

The semiconductor industry is entering a new era, driven by advancements in memory technology and the growing influence of artificial…

Exploring essential concepts in Formal Verification

What is a witness? is it the same as a counterexample? A witness is a sequence of inputs that demonstrates…

Assertions and benefits of abstractions in Formal Verification

How are assertions specified? Assertions are typically specified using languages like SystemVerilog Assertions (SVA) or Property Specification Language (PSL). These…

Understanding Formal Verification

What is formal verification? Formal verification is a method to ensure that a hardware design behaves as intended by using…

Jump-Start Your UVM Journey with UVM Framework (UVMF)

Bob Oden shares insights on how the Universal Verification Methodology Framework (UVMF) is revolutionizing the verification landscape. UVMF is an advanced toolset that…

Verification Challenges and Solutions for Multi-Die Systems (UCIe) 

Introduction Multi-die systems accelerate the scaling of system functionality, reduce risk, and facilitate the creation of new product variants. However,…

Accelerating Verification of Computational Storage Designs (NVMe)

Introduction Computational storage is revolutionizing data storage by embedding computational capabilities within storage devices, significantly boosting system efficiency by reducing…

Simulation is Key in design verification process

The importance of simulation in the pursuit of absolute speed!

A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process