IEEE Honors Tom Fitzpatrick

At the IEEE Standards Association’s 2022 winter awards ceremony, Tom Fitzpatrick was honored for his leadership in standards development and…

The UVM type-based Factory can print base and derived objects

UVM Factory Revealed, Part 1

Introduction When you first learn UVM, most of the concepts make sense, even if you are new to Object-Oriented Programming….

Safety Lifecycle Components

Safety Lifecycle Evaluation Part 3: A productivity evolution

Integration made the difference. The global consulting firm that was asked to conduct the safety lifecycle study advised the company…

ISO 26262

ISO 26262…the tale of Transient and Permanent Faults

Introduction Are you designing to the ISO 26262 standard and trying to decide if your design is safe from random…

Three ice cream cones, vanilla, chocolate, and strawberry

Does Your UVM Flavor Have Sprinkles?

Introduction UVM is a standard, so that means that every company writes their testbenches the same, universally interchangeable, right? Not…

A pool of specialized classes

Dig a Pool of Specialized SystemVerilog Classes

Introduction SystemVerilog classes are a great way to encapsulate both variables and the routines that operates on them. What if…

Implicit handle: this

SystemVerilog: Implicit handles

Introduction In the last blog post [SC(SECL1] Farmer Ted asked you to keep track of his animals and you wrote some…

SystemVerilog: Class Member Visibility

SystemVerilog: Class Member Visibility

Introduction Farmer Ted wants to keep track of the animals on his property and asks you to write the code….

Connect test module with interface to design with individual ports

SystemVerilog: What is a Virtual Interface?

When I learned the SystemVerilog verification features, one concept had me baffled – virtual interfaces. What are these and why…