Making formal property checking easy to use

Making formal property checking easy to use

For years one of the objectives in EDA has been to make formal property checking easy to use and its…

Redefining Verification Performance (Part 1)

Redefining Verification Performance (Part 1)

What does the word performance mean to you? Speed? Well, obviously speed is an important characteristic. Yet, if the team…

SystemVerilog Coding Guidelines: Package import versus `include

SystemVerilog Coding Guidelines: Package import versus `include

Another frequently asked question: Should I import my classes from a package or `include them? To answer this properly, you…

The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)

The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)

Now that the Accellera VIP-TSC has released UVM-EA, effectively narrowing the choice of verification methodologies to UVM or OVM, many…

New Verification Academy Advanced OVM (&UVM) Module

New Verification Academy Advanced OVM (&UVM) Module

I’ve always loved the Chinese proverb, “Give a man a fish and you feed him for a day. Teach a…

OVM/UVM @DAC: The Dog That Didn’t Bark

OVM/UVM @DAC: The Dog That Didn’t Bark

In the classic Sherlock Holmes story, “Silver Blaze,” Holmes realizes that the family dog didn’t bark when the suspect entered…

DAC: Day 1; An Ode to an Old Friend

DAC: Day 1; An Ode to an Old Friend

Denali Finale While I ponder the hundreds of partners I work with to support a vibrant ecosystem of ModelSim and…

UVM: Joint Statement Issued by Mentor, Cadence & Synopsys

UVM: Joint Statement Issued by Mentor, Cadence & Synopsys

DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys The full statement can be read at EDA…

Static Verification

Static Verification

After spending years verifying ASICs with dynamic simulation, I started working on static verification 10 years ago in a startup…