New Verification Horizons: Methodologies Don’t Have to be Scary

New Verification Horizons: Methodologies Don’t Have to be Scary

Hi Everyone, Just wanted to let you know that the latest edition of our Verification Horizons newsletter is available here….

The Survey Says: Verification Planning

The Survey Says: Verification Planning

As the saying goes: Those who fail to plan, plan to fail. With that said, I am excited to announce…

Towards UVM Register Package Interoperability

Towards UVM Register Package Interoperability

23rd Synopsys EDA Interoperability Forum Features a Verification Session with focus on the UVM Register Package As readers of the…

UVM: Giving Users What They Want

UVM: Giving Users What They Want

Technorati Tags: UVM,SystemVerilog,RAL,OVM The development of UVM in the Accellera VIP-TSC brings up, yet again, the age-old philosophical question: should…

UVM Takes Shape in the Accellera VIP-TSC

UVM Takes Shape in the Accellera VIP-TSC

UVM is Taking Shape While you have all been happily verifying your complex SoCs the Accellera VIP Technical Subcommittee (VIP-TSC),…

Accellera VIP-TSC Selects RAL for UVM 1.0 Register Package

Accellera VIP-TSC Selects RAL for UVM 1.0 Register Package

Mentor/Synopsys Collaboration Bears Fruit Two weeks back I shared information in a blog on collaboration between Mentor Graphics and Synopsys…

OVM Cookbook Available from OVMWorld.org

OVM Cookbook Available from OVMWorld.org

Companion OVM Cookbook Examples Kit also offered for download Several months ago, the OVM Cookbook and the Examples Kit were…

UVM Register Package Candidate News

UVM Register Package Candidate News

Mentor Announces Collaboration with Synopsys on Joint Register Package Candidate Mentor has recently teamed with Synopsys to collaborate on the…