Prologue: The 2012 Wilson Research Group Functional Verification Study

Prologue: The 2012 Wilson Research Group Functional Verification Study

This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional…

Even More UVM Debug in Questa 10.2

Even More UVM Debug in Questa 10.2

We’re really excited about the recent Questa 10.2 release, and I’m sure you’ll be just as excited when you check…

IEEE Approves New Low Power Standard

IEEE Approves New Low Power Standard

IEEE 1801™-2013 Enters Pre-Publish Phase The completion and approval of electronic design automation standards has seemed to be the order…

Verification Horizons DVCon Issue Now Available

Verification Horizons DVCon Issue Now Available

Hi Everyone, Just wanted to let you all know that the new issue of Verification Horizons is now available. You…

IEEE 1800™-2012 SystemVerilog Standard Is Published

IEEE 1800™-2012 SystemVerilog Standard Is Published

Download the standard now – at no charge! The IEEE has published the latest update to the SystemVerilog standard.  And…

See You at DVCon 2013!

See You at DVCon 2013!

Learn about new standards, industry surveys and trends This year’s DVCon is set and if you have not yet registered,…

Get Ready for SystemVerilog 2012

Get Ready for SystemVerilog 2012

The latest revision of the IEEE 1800-2012 SystemVerilog Language Reference Manual (LRM) is about to hit the press; though I…

VHDL Update Comes to Verification Academy!

VHDL Update Comes to Verification Academy!

VHDL-2008 Explained Via 7 Course Modules For some time now a dedicated group of engineers have defined and standardized an…

IEEE Approves Revised SystemVerilog Standard

IEEE Approves Revised SystemVerilog Standard

IEEE Std. 1800™-2012 Officially Ratified The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft…