Instant Replay for Debugging SoC Level Simulations

Instant Replay for Debugging SoC Level Simulations

Instant Replay Offers Multiple Views at Any Speed If you’ve watched any professional sporting event on television lately, you’ve seen…

2011 IEEE Design Automation Standards Awards

2011 IEEE Design Automation Standards Awards

The DASC Participates in IEEE Standards Association Gala Event The IEEE Computer Society Design Automation Standards Committee (DASC) participated in…

Getting started with the UVM – Using the Register Modeling package

Getting started with the UVM – Using the Register Modeling package

Adopting SystemVerilog can be challenging to some, and learning the UVM at the same time might seem overwhelming. There is…

TLM Becomes an IEEE Standard

TLM Becomes an IEEE Standard

IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced…

Worlds Standards Day 2011

Worlds Standards Day 2011

Creating Confidence Globally Today, 14 October 2011, is the day the world celebrates standards.  The leadership of the IEC, ISO…

VHS or Betamax?

VHS or Betamax?

Legacy’s Luster Lost As a follow-on to my last blog, where I shared information about Harry Foster speaking live about…

Verification Issues Take Center Stage

Verification Issues Take Center Stage

Is Legacy Holding You Back? Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on…

New UVM Recipe-of-the-Month: Sequence Layering

New UVM Recipe-of-the-Month: Sequence Layering

I’m excited to announce that our second UVM Recipe-of-the-Month Webinar, “Sequence Layering,” will be presented on Thursday, September 15, at…

Combining Intelligent Testbench Automation with Constrained Random Testing

Combining Intelligent Testbench Automation with Constrained Random Testing

Who Doesn’t Like Faster? In my last blog post I introduced new technology called Intelligent Testbench Automation (“iTBA”).  It’s generating…